riscv/sim.cc

   1 // See LICENSE for license details.
   2
   3 #include "sim.h"
   4 #include "htif.h"
   5 #include <map>
   6 #include <iostream>
   7 #include <sstream>
   8 #include <climits>
   9 #include <cstdlib>
  10 #include <cassert>
  11 #include <signal.h>
  12
  13 volatile bool ctrlc_pressed = false;
  14 static void handle_signal(int sig)
  15 {
  16   if (ctrlc_pressed)
  17     exit(-1);
  18   ctrlc_pressed = true;
  19   signal(sig, &handle_signal);
  20 }
  21
  22 sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
  23              const std::vector<std::string>& args)
  24   : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
  25     rtc(0), current_step(0), current_proc(0), debug(false)
  26 {
  27   signal(SIGINT, &handle_signal);
  28   // allocate target machine's memory, shrinking it as necessary
  29   // until the allocation succeeds
  30   size_t memsz0 = (size_t)mem_mb << 20;
  31   size_t quantum = 1L << 20;
  32   if (memsz0 == 0)
  33     memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
  34
  35   memsz = memsz0;
  36   while ((mem = (char*)calloc(1, memsz)) == NULL)
  37     memsz = (size_t)(memsz*0.9)/quantum*quantum;
  38
  39   if (memsz != memsz0)
  40     fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
  41             (unsigned long)memsz, (unsigned long)memsz0);
  42
  43   debug_mmu = new mmu_t(mem, memsz);
  44
  45   for (size_t i = 0; i < procs.size(); i++)
  46     procs[i] = new processor_t(isa, this, i);
  47
  48   make_config_string();
  49 }
  50
  51 sim_t::~sim_t()
  52 {
  53   for (size_t i = 0; i < procs.size(); i++)
  54     delete procs[i];
  55   delete debug_mmu;
  56   free(mem);
  57 }
  58
  59 reg_t sim_t::get_scr(int which)
  60 {
  61   switch (which)
  62   {
  63     case 0: return procs.size();
  64     case 1: return memsz >> 20;
  65     default: return -1;
  66   }
  67 }
  68
  69 int sim_t::run()
  70 {
  71   if (!debug && log)
  72     set_procs_debug(true);
  73   while (htif->tick())
  74   {
  75     if (debug || ctrlc_pressed)
  76       interactive();
  77     else
  78       step(INTERLEAVE);
  79   }
  80   return htif->exit_code();
  81 }
  82
  83 void sim_t::step(size_t n)
  84 {
  85   for (size_t i = 0, steps = 0; i < n; i += steps)
  86   {
  87     steps = std::min(n - i, INTERLEAVE - current_step);
  88     procs[current_proc]->step(steps);
  89
  90     current_step += steps;
  91     if (current_step == INTERLEAVE)
  92     {
  93       current_step = 0;
  94       procs[current_proc]->yield_load_reservation();
  95       if (++current_proc == procs.size()) {
  96         current_proc = 0;
  97         rtc += INTERLEAVE / INSNS_PER_RTC_TICK;
  98       }
  99
 100       htif->tick();
 101     }
 102   }
 103 }
 104
 105 bool sim_t::running()
 106 {
 107   for (size_t i = 0; i < procs.size(); i++)
 108     if (procs[i]->running())
 109       return true;
 110   return false;
 111 }
 112
 113 void sim_t::stop()
 114 {
 115   procs[0]->state.tohost = 1;
 116   while (htif->tick())
 117     ;
 118 }
 119
 120 void sim_t::set_debug(bool value)
 121 {
 122   debug = value;
 123 }
 124
 125 void sim_t::set_log(bool value)
 126 {
 127   log = value;
 128 }
 129
 130 void sim_t::set_histogram(bool value)
 131 {
 132   histogram_enabled = value;
 133   for (size_t i = 0; i < procs.size(); i++) {
 134     procs[i]->set_histogram(histogram_enabled);
 135   }
 136 }
 137
 138 void sim_t::set_procs_debug(bool value)
 139 {
 140   for (size_t i=0; i< procs.size(); i++)
 141     procs[i]->set_debug(value);
 142 }
 143
 144 bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
 145 {
 146   if (addr + len < addr)
 147     return false;
 148   return bus.load(addr, len, bytes);
 149 }
 150
 151 bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 152 {
 153   if (addr + len < addr)
 154     return false;
 155   return bus.store(addr, len, bytes);
 156 }
 157
 158 void sim_t::make_config_string()
 159 {
 160   size_t csr_size = NCSR * 16 /* RV128 */;
 161   size_t device_tree_addr = memsz;
 162   size_t cpu_addr = memsz + csr_size;
 163
 164   std::stringstream s;
 165   s << std::hex <<
 166         "platform {\n"
 167         "  vendor ucb;\n"
 168         "  arch spike;\n"
 169         "};\n"
 170         "ram {\n"
 171         "  0 {\n"
 172         "    addr 0;\n"
 173         "    size 0x" << memsz << ";\n"
 174         "  };\n"
 175         "};\n"
 176         "core {\n";
 177   for (size_t i = 0; i < procs.size(); i++) {
 178     s <<
 179         "  " << i << " {\n"
 180         "    " << "0 {\n" << // hart 0 on core i
 181         "      isa " << procs[i]->isa_string << ";\n"
 182         "      addr 0x" << cpu_addr << ";\n"
 183         "    };\n"
 184         "  };\n";
 185     bus.add_device(cpu_addr, procs[i]);
 186     cpu_addr += csr_size;
 187   }
 188   s <<  "};\n";
 189
 190   std::string str = s.str();
 191   std::vector<char> vec(str.begin(), str.end());
 192   vec.push_back(0);
 193   assert(vec.size() <= csr_size);
 194   config_string.reset(new rom_device_t(vec));
 195   bus.add_device(memsz, config_string.get());
 196 }