riscv/sim.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_SIM_H
   4 #define _RISCV_SIM_H
   5
   6 #include <vector>
   7 #include <string>
   8 #include <memory>
   9 #include "processor.h"
  10 #include "devices.h"
  11
  12 class htif_isasim_t;
  13 class mmu_t;
  14
  15 // this class encapsulates the processors and memory in a RISC-V machine.
  16 class sim_t
  17 {
  18 public:
  19   sim_t(const char* isa, size_t _nprocs, size_t mem_mb,
  20         const std::vector<std::string>& htif_args);
  21   ~sim_t();
  22
  23   // run the simulation to completion
  24   int run();
  25   bool running();
  26   void stop();
  27   void set_debug(bool value);
  28   void set_log(bool value);
  29   void set_histogram(bool value);
  30   void set_procs_debug(bool value);
  31   htif_isasim_t* get_htif() { return htif.get(); }
  32   const char* get_config_string() { return config_string.c_str(); }
  33
  34   // returns the number of processors in this simulator
  35   size_t num_cores() { return procs.size(); }
  36   processor_t* get_core(size_t i) { return procs.at(i); }
  37
  38 private:
  39   std::unique_ptr<htif_isasim_t> htif;
  40   char* mem; // main memory
  41   size_t memsz; // memory size in bytes
  42   mmu_t* debug_mmu;  // debug port into main memory
  43   std::vector<processor_t*> procs;
  44   std::string config_string;
  45   std::unique_ptr<rom_device_t> boot_rom;
  46   std::unique_ptr<rtc_t> rtc;
  47   bus_t bus;
  48
  49   processor_t* get_core(const std::string& i);
  50   void step(size_t n); // step through simulation
  51   static const size_t INTERLEAVE = 5000;
  52   static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core
  53   size_t current_step;
  54   size_t current_proc;
  55   bool debug;
  56   bool log;
  57   bool histogram_enabled; // provide a histogram of PCs
  58
  59   // memory-mapped I/O routines
  60   bool addr_is_mem(reg_t addr) {
  61     return addr >= DRAM_BASE && addr < DRAM_BASE + memsz;
  62   }
  63   char* addr_to_mem(reg_t addr) { return mem + addr - DRAM_BASE; }
  64   reg_t mem_to_addr(char* x) { return x - mem + DRAM_BASE; }
  65   bool mmio_load(reg_t addr, size_t len, uint8_t* bytes);
  66   bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes);
  67   void make_config_string();
  68
  69   // presents a prompt for introspection into the simulation
  70   void interactive();
  71
  72   // functions that help implement interactive()
  73   void interactive_help(const std::string& cmd, const std::vector<std::string>& args);
  74   void interactive_quit(const std::string& cmd, const std::vector<std::string>& args);
  75   void interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy);
  76   void interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args);
  77   void interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args);
  78   void interactive_reg(const std::string& cmd, const std::vector<std::string>& args);
  79   void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args);
  80   void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args);
  81   void interactive_pc(const std::string& cmd, const std::vector<std::string>& args);
  82   void interactive_mem(const std::string& cmd, const std::vector<std::string>& args);
  83   void interactive_str(const std::string& cmd, const std::vector<std::string>& args);
  84   void interactive_until(const std::string& cmd, const std::vector<std::string>& args);
  85   reg_t get_reg(const std::vector<std::string>& args);
  86   reg_t get_freg(const std::vector<std::string>& args);
  87   reg_t get_mem(const std::vector<std::string>& args);
  88   reg_t get_pc(const std::vector<std::string>& args);
  89   reg_t get_tohost(const std::vector<std::string>& args);
  90
  91   friend class htif_isasim_t;
  92   friend class processor_t;
  93   friend class mmu_t;
  94 };
  95
  96 extern volatile bool ctrlc_pressed;
  97
  98 #endif