riscv/sim.h

   1 #ifndef _RISCV_SIM_H
   2 #define _RISCV_SIM_H
   3
   4 #include <vector>
   5 #include <string>
   6 #include "processor.h"
   7
   8 const long MEMSIZE = 0x100000000;
   9
  10 class appserver_link_t;
  11
  12 class sim_t
  13 {
  14 public:
  15   sim_t(int _nprocs, size_t _memsz, appserver_link_t* _applink);
  16   ~sim_t();
  17   void run(bool debug);
  18
  19   void set_tohost(reg_t val);
  20   reg_t get_fromhost();
  21
  22 private:
  23   // global architected state
  24   reg_t tohost;
  25   reg_t fromhost;
  26
  27   appserver_link_t* applink;
  28
  29   size_t memsz;
  30   char* mem;
  31   std::vector<processor_t> procs;
  32
  33   void step_all(size_t n, size_t interleave, bool noisy);
  34
  35   void interactive_quit(const std::vector<std::string>& args);
  36
  37   void interactive_run(const std::vector<std::string>& args, bool noisy);
  38   void interactive_run_noisy(const std::vector<std::string>& args);
  39   void interactive_run_silent(const std::vector<std::string>& args);
  40
  41   void interactive_run_proc(const std::vector<std::string>& args, bool noisy);
  42   void interactive_run_proc_noisy(const std::vector<std::string>& args);
  43   void interactive_run_proc_silent(const std::vector<std::string>& args);
  44
  45   void interactive_reg(const std::vector<std::string>& args);
  46   void interactive_fregs(const std::vector<std::string>& args);
  47   void interactive_fregd(const std::vector<std::string>& args);
  48   void interactive_mem(const std::vector<std::string>& args);
  49   void interactive_until(const std::vector<std::string>& args);
  50
  51   reg_t get_reg(const std::vector<std::string>& args);
  52   reg_t get_freg(const std::vector<std::string>& args);
  53   reg_t get_mem(const std::vector<std::string>& args);
  54   reg_t get_pc(const std::vector<std::string>& args);
  55
  56   friend class appserver_link_t;
  57 };
  58
  59 #endif