riscv/sim.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_SIM_H
   4 #define _RISCV_SIM_H
   5
   6 #include <vector>
   7 #include <string>
   8 #include <memory>
   9 #include "processor.h"
  10 #include "mmu.h"
  11
  12 class htif_isasim_t;
  13
  14 // this class encapsulates the processors and memory in a RISC-V machine.
  15 class sim_t
  16 {
  17 public:
  18   sim_t(const char* isa, size_t _nprocs, size_t mem_mb,
  19         const std::vector<std::string>& htif_args);
  20   ~sim_t();
  21
  22   // run the simulation to completion
  23   int run();
  24   bool running();
  25   void stop();
  26   void set_debug(bool value);
  27   void set_histogram(bool value);
  28   void set_procs_debug(bool value);
  29   htif_isasim_t* get_htif() { return htif.get(); }
  30
  31   // deliver an IPI to a specific processor
  32   void send_ipi(reg_t who);
  33
  34   // returns the number of processors in this simulator
  35   size_t num_cores() { return procs.size(); }
  36   processor_t* get_core(size_t i) { return procs.at(i); }
  37
  38   // read one of the system control registers
  39   reg_t get_scr(int which);
  40
  41 private:
  42   std::unique_ptr<htif_isasim_t> htif;
  43   char* mem; // main memory
  44   size_t memsz; // memory size in bytes
  45   mmu_t* debug_mmu;  // debug port into main memory
  46   std::vector<processor_t*> procs;
  47
  48   void step(size_t n); // step through simulation
  49   static const size_t INTERLEAVE = 5000;
  50   static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core
  51   reg_t rtc;
  52   size_t current_step;
  53   size_t current_proc;
  54   bool debug;
  55   bool histogram_enabled; // provide a histogram of PCs
  56
  57   // presents a prompt for introspection into the simulation
  58   void interactive();
  59
  60   // functions that help implement interactive()
  61   void interactive_help(const std::string& cmd, const std::vector<std::string>& args);
  62   void interactive_quit(const std::string& cmd, const std::vector<std::string>& args);
  63   void interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy);
  64   void interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args);
  65   void interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args);
  66   void interactive_reg(const std::string& cmd, const std::vector<std::string>& args);
  67   void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args);
  68   void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args);
  69   void interactive_mem(const std::string& cmd, const std::vector<std::string>& args);
  70   void interactive_str(const std::string& cmd, const std::vector<std::string>& args);
  71   void interactive_until(const std::string& cmd, const std::vector<std::string>& args);
  72   reg_t get_reg(const std::vector<std::string>& args);
  73   reg_t get_freg(const std::vector<std::string>& args);
  74   reg_t get_mem(const std::vector<std::string>& args);
  75   reg_t get_pc(const std::vector<std::string>& args);
  76   reg_t get_tohost(const std::vector<std::string>& args);
  77
  78   friend class htif_isasim_t;
  79   friend class processor_t;
  80 };
  81
  82 extern volatile bool ctrlc_pressed;
  83
  84 #endif