1 // See LICENSE for license details.
8 #include "debug_module.h"
9 #include <fesvr/htif.h>
10 #include <fesvr/context.h>
16 class remote_bitbang_t
;
18 // this class encapsulates the processors and memory in a RISC-V machine.
19 class sim_t
: public htif_t
22 sim_t(const char* isa
, size_t _nprocs
, size_t mem_mb
, bool halted
,
23 const std::vector
<std::string
>& args
);
26 // run the simulation to completion
28 void set_debug(bool value
);
29 void set_log(bool value
);
30 void set_histogram(bool value
);
31 void set_procs_debug(bool value
);
32 void set_remote_bitbang(remote_bitbang_t
* remote_bitbang
) {
33 this->remote_bitbang
= remote_bitbang
;
35 const char* get_dts() { return dts
.c_str(); }
36 processor_t
* get_core(size_t i
) { return procs
.at(i
); }
37 unsigned nprocs() const { return procs
.size(); }
39 debug_module_t debug_module
;
42 char* mem
; // main memory
43 size_t memsz
; // memory size in bytes
44 mmu_t
* debug_mmu
; // debug port into main memory
45 std::vector
<processor_t
*> procs
;
47 std::unique_ptr
<rom_device_t
> boot_rom
;
48 std::unique_ptr
<clint_t
> clint
;
51 processor_t
* get_core(const std::string
& i
);
52 void step(size_t n
); // step through simulation
53 static const size_t INTERLEAVE
= 5000;
54 static const size_t INSNS_PER_RTC_TICK
= 100; // 10 MHz clock for 1 BIPS core
55 static const size_t CPU_HZ
= 1000000000; // 1GHz CPU
60 bool histogram_enabled
; // provide a histogram of PCs
61 remote_bitbang_t
* remote_bitbang
;
63 // memory-mapped I/O routines
64 bool addr_is_mem(reg_t addr
) {
65 return addr
>= DRAM_BASE
&& addr
< DRAM_BASE
+ memsz
;
67 char* addr_to_mem(reg_t addr
) { return mem
+ addr
- DRAM_BASE
; }
68 reg_t
mem_to_addr(char* x
) { return x
- mem
+ DRAM_BASE
; }
69 bool mmio_load(reg_t addr
, size_t len
, uint8_t* bytes
);
70 bool mmio_store(reg_t addr
, size_t len
, const uint8_t* bytes
);
73 // presents a prompt for introspection into the simulation
76 // functions that help implement interactive()
77 void interactive_help(const std::string
& cmd
, const std::vector
<std::string
>& args
);
78 void interactive_quit(const std::string
& cmd
, const std::vector
<std::string
>& args
);
79 void interactive_run(const std::string
& cmd
, const std::vector
<std::string
>& args
, bool noisy
);
80 void interactive_run_noisy(const std::string
& cmd
, const std::vector
<std::string
>& args
);
81 void interactive_run_silent(const std::string
& cmd
, const std::vector
<std::string
>& args
);
82 void interactive_reg(const std::string
& cmd
, const std::vector
<std::string
>& args
);
83 void interactive_freg(const std::string
& cmd
, const std::vector
<std::string
>& args
);
84 void interactive_fregs(const std::string
& cmd
, const std::vector
<std::string
>& args
);
85 void interactive_fregd(const std::string
& cmd
, const std::vector
<std::string
>& args
);
86 void interactive_pc(const std::string
& cmd
, const std::vector
<std::string
>& args
);
87 void interactive_mem(const std::string
& cmd
, const std::vector
<std::string
>& args
);
88 void interactive_str(const std::string
& cmd
, const std::vector
<std::string
>& args
);
89 void interactive_until(const std::string
& cmd
, const std::vector
<std::string
>& args
);
90 reg_t
get_reg(const std::vector
<std::string
>& args
);
91 freg_t
get_freg(const std::vector
<std::string
>& args
);
92 reg_t
get_mem(const std::vector
<std::string
>& args
);
93 reg_t
get_pc(const std::vector
<std::string
>& args
);
95 friend class processor_t
;
99 friend void sim_thread_main(void*);
106 void read_chunk(addr_t taddr
, size_t len
, void* dst
);
107 void write_chunk(addr_t taddr
, size_t len
, const void* src
);
108 size_t chunk_align() { return 8; }
109 size_t chunk_max_size() { return 8; }
112 extern volatile bool ctrlc_pressed
;