riscv/sim.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_SIM_H
   4 #define _RISCV_SIM_H
   5
   6 #include "processor.h"
   7 #include "devices.h"
   8 #include "debug_module.h"
   9 #include <fesvr/htif.h>
  10 #include <fesvr/context.h>
  11 #include <vector>
  12 #include <string>
  13 #include <memory>
  14
  15 class mmu_t;
  16 class remote_bitbang_t;
  17
  18 // this is the interface to the simulator used by the processors and memory
  19 class simif_t
  20 {
  21 public:
  22   // should return NULL for MMIO addresses
  23   virtual char* addr_to_mem(reg_t addr) = 0;
  24   // used for MMIO addresses
  25   virtual bool mmio_load(reg_t addr, size_t len, uint8_t* bytes) = 0;
  26   virtual bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes) = 0;
  27   // Callback for processors to let the simulation know they were reset.
  28   virtual void proc_reset(unsigned id) = 0;
  29 };
  30
  31 // this class encapsulates the processors and memory in a RISC-V machine.
  32 class sim_t : public htif_t, public simif_t
  33 {
  34 public:
  35   sim_t(const char* isa, size_t _nprocs,  bool halted, reg_t start_pc,
  36         std::vector<std::pair<reg_t, mem_t*>> mems,
  37         const std::vector<std::string>& args, const std::vector<int> hartids,
  38         unsigned progsize, unsigned max_bus_master_bits, bool require_authentication);
  39   ~sim_t();
  40
  41   // run the simulation to completion
  42   int run();
  43   void set_debug(bool value);
  44   void set_log(bool value);
  45   void set_histogram(bool value);
  46   void set_procs_debug(bool value);
  47   void set_remote_bitbang(remote_bitbang_t* remote_bitbang) {
  48     this->remote_bitbang = remote_bitbang;
  49   }
  50   const char* get_dts() { if (dts.empty()) reset(); return dts.c_str(); }
  51   processor_t* get_core(size_t i) { return procs.at(i); }
  52   unsigned nprocs() const { return procs.size(); }
  53
  54   // Callback for processors to let the simulation know they were reset.
  55   void proc_reset(unsigned id);
  56
  57 private:
  58   std::vector<std::pair<reg_t, mem_t*>> mems;
  59   mmu_t* debug_mmu;  // debug port into main memory
  60   std::vector<processor_t*> procs;
  61   reg_t start_pc;
  62   std::string dts;
  63   std::unique_ptr<rom_device_t> boot_rom;
  64   std::unique_ptr<clint_t> clint;
  65   bus_t bus;
  66
  67   processor_t* get_core(const std::string& i);
  68   void step(size_t n); // step through simulation
  69   static const size_t INTERLEAVE = 5000;
  70   static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core
  71   static const size_t CPU_HZ = 1000000000; // 1GHz CPU
  72   size_t current_step;
  73   size_t current_proc;
  74   bool debug;
  75   bool log;
  76   bool histogram_enabled; // provide a histogram of PCs
  77   remote_bitbang_t* remote_bitbang;
  78
  79   // memory-mapped I/O routines
  80   char* addr_to_mem(reg_t addr);
  81   bool mmio_load(reg_t addr, size_t len, uint8_t* bytes);
  82   bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes);
  83   void make_dtb();
  84
  85   // presents a prompt for introspection into the simulation
  86   void interactive();
  87
  88   // functions that help implement interactive()
  89   void interactive_help(const std::string& cmd, const std::vector<std::string>& args);
  90   void interactive_quit(const std::string& cmd, const std::vector<std::string>& args);
  91   void interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy);
  92   void interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args);
  93   void interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args);
  94   void interactive_reg(const std::string& cmd, const std::vector<std::string>& args);
  95   void interactive_freg(const std::string& cmd, const std::vector<std::string>& args);
  96   void interactive_fregs(const std::string& cmd, const std::vector<std::string>& args);
  97   void interactive_fregd(const std::string& cmd, const std::vector<std::string>& args);
  98   void interactive_pc(const std::string& cmd, const std::vector<std::string>& args);
  99   void interactive_mem(const std::string& cmd, const std::vector<std::string>& args);
 100   void interactive_str(const std::string& cmd, const std::vector<std::string>& args);
 101   void interactive_until(const std::string& cmd, const std::vector<std::string>& args);
 102   reg_t get_reg(const std::vector<std::string>& args);
 103   freg_t get_freg(const std::vector<std::string>& args);
 104   reg_t get_mem(const std::vector<std::string>& args);
 105   reg_t get_pc(const std::vector<std::string>& args);
 106
 107   friend class processor_t;
 108   friend class mmu_t;
 109   friend class debug_module_t;
 110
 111   // htif
 112   friend void sim_thread_main(void*);
 113   void main();
 114
 115   context_t* host;
 116   context_t target;
 117   void reset();
 118   void idle();
 119   void read_chunk(addr_t taddr, size_t len, void* dst);
 120   void write_chunk(addr_t taddr, size_t len, const void* src);
 121   size_t chunk_align() { return 8; }
 122   size_t chunk_max_size() { return 8; }
 123
 124 public:
 125   // Initialize this after procs, because in debug_module_t::reset() we
 126   // enumerate processors, which segfaults if procs hasn't been initialized
 127   // yet.
 128   debug_module_t debug_module;
 129 };
 130
 131 extern volatile bool ctrlc_pressed;
 132
 133 #endif