riscv/sv_decode.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_SV_DECODE_H
   4 #define _RISCV_SV_DECODE_H
   5
   6 #include "sv.h"
   7 #include "decode.h"
   8 #include "processor.h"
   9
  10 #define REG_RD 0x1
  11 #define REG_RS1 0x2
  12 #define REG_RS2 0x4
  13 #define REG_RS3 0x8
  14 #define REG_RVC_RS1 0x10
  15 #define REG_RVC_RS2 0x20
  16 #define REG_RVC_RS1S 0x40
  17 #define REG_RVC_RS2S 0x80
  18
  19
  20 class sv_insn_t: public insn_t
  21 {
  22 public:
  23   sv_insn_t(processor_t *pr, insn_bits_t bits, unsigned int f,
  24             uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3,
  25             int &o_rd, int &o_rs1, int &o_rs2, int &o_rs3) :
  26             insn_t(bits), p(pr), vloop_continue(false), fimap(f),
  27             offs_rd(o_rd), offs_rs1(o_rs1), offs_rs2(o_rs2), offs_rs3(o_rs3),
  28             prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3) {}
  29   uint64_t rd () { return predicated(_rd (), offs_rd, prd); }
  30   uint64_t rs1() { return predicated(_rs1(), offs_rs1, prs1); }
  31   uint64_t rs2() { return predicated(_rs2(), offs_rs2, prs2); }
  32   uint64_t rs3() { return predicated(_rs3(), offs_rs3, prs3); }
  33   uint64_t rvc_rs1 () { return predicated(_rvc_rs1 (), offs_rs1, prs1); }
  34   uint64_t rvc_rs1s() { return predicated(_rvc_rs1s(), offs_rs1, prs1); }
  35   uint64_t rvc_rs2 () { return predicated(_rvc_rs2 (), offs_rs2, prs2); }
  36   uint64_t rvc_rs2s() { return predicated(_rvc_rs2s(), offs_rs2, prs2); }
  37
  38   uint64_t _rd () { return _remap(insn_t::rd (), fimap & REG_RD , offs_rd); }
  39   uint64_t _rs1() { return _remap(insn_t::rs1(), fimap & REG_RS1, offs_rs1); }
  40   uint64_t _rs2() { return _remap(insn_t::rs2(), fimap & REG_RS2, offs_rs2); }
  41   uint64_t _rs3() { return _remap(insn_t::rs3(), fimap & REG_RS3, offs_rs3); }
  42   uint64_t _rvc_rs1 () { return _remap(insn_t::rvc_rs1(), fimap & REG_RVC_RS1,
  43                                        offs_rs1); }
  44   uint64_t _rvc_rs1s() { return _remap(insn_t::rvc_rs1s(), fimap & REG_RVC_RS1S,
  45                                        offs_rs1); }
  46   uint64_t _rvc_rs2 () { return _remap(insn_t::rvc_rs2(), fimap & REG_RVC_RS2,
  47                                        offs_rs2); }
  48   uint64_t _rvc_rs2s() { return _remap(insn_t::rvc_rs2s(), fimap & REG_RVC_RS2S,
  49                                        offs_rs2); }
  50
  51   bool sv_check_reg(bool intreg, uint64_t reg);
  52   sv_reg_entry* get_regentry(uint64_t reg, bool isint);
  53   sv_pred_entry* get_predentry(uint64_t reg, bool isint);
  54   reg_t predicate(uint64_t reg, bool isint, bool &zeroing);
  55
  56   void reset_vloop_check(void) { vloop_continue = false; }
  57   bool stop_vloop(void);
  58
  59   processor_t *p;
  60 private:
  61   bool vloop_continue;
  62   unsigned int fimap;
  63   int &offs_rd;
  64   int &offs_rs1;
  65   int &offs_rs2;
  66   int &offs_rs3;
  67   uint64_t &prd;
  68   uint64_t &prs1;
  69   uint64_t &prs2;
  70   uint64_t &prs3;
  71
  72   // remaps the register through the lookup table.
  73   // will need to take the current loop index/offset somehow
  74   uint64_t remap(uint64_t reg, bool isint, int &offs);
  75
  76   // cached version of remap: if remap is called multiple times
  77   // by an emulated instruction it would increment the loop offset
  78   // before it's supposed to.
  79   uint64_t _remap(uint64_t reg, bool isint, int &offs)
  80   {
  81     if (sv_check_reg(isint, reg))
  82     {
  83         vloop_continue = true;
  84     }
  85     return remap(reg, isint, offs);
  86   }
  87
  88   uint64_t predicated(uint64_t reg, int offs, uint64_t pred);
  89 };
  90
  91 #endif