Set tval to 0 on traps with no specified tval
[riscv-isa-sim.git] / riscv / tracer.h
1 // See LICENSE for license details.
2
3 #ifndef _RISCV_TRACER_H
4 #define _RISCV_TRACER_H
5
6 #include "processor.h"
7
8 static inline void trace_opcode(processor_t* p, insn_bits_t opc, insn_t insn) {
9 }
10
11 #endif