add BSD license
[riscv-isa-sim.git] / riscv / trap.h
1 // See LICENSE for license details.
2
3 #ifndef _RISCV_TRAP_H
4 #define _RISCV_TRAP_H
5
6 #define TRAP_LIST \
7 DECLARE_TRAP(instruction_address_misaligned), \
8 DECLARE_TRAP(instruction_access_fault), \
9 DECLARE_TRAP(illegal_instruction), \
10 DECLARE_TRAP(privileged_instruction), \
11 DECLARE_TRAP(fp_disabled), \
12 DECLARE_TRAP(reserved0), \
13 DECLARE_TRAP(syscall), \
14 DECLARE_TRAP(breakpoint), \
15 DECLARE_TRAP(load_address_misaligned), \
16 DECLARE_TRAP(store_address_misaligned), \
17 DECLARE_TRAP(load_access_fault), \
18 DECLARE_TRAP(store_access_fault), \
19 DECLARE_TRAP(vector_disabled), \
20 DECLARE_TRAP(vector_bank), \
21 DECLARE_TRAP(vector_illegal_instruction), \
22 DECLARE_TRAP(reserved1), \
23
24 #define DECLARE_TRAP(x) trap_##x
25 enum trap_t
26 {
27 TRAP_LIST
28 NUM_TRAPS
29 };
30 #undef DECLARE_TRAP
31
32 struct interrupt_t { interrupt_t(int which) : i(which) {} int i; };
33 struct halt_t {}; // thrown to stop the processor from running
34
35 extern "C" const char* trap_name(trap_t t);
36
37 #endif