spike/disasm.cc

   1 // See LICENSE for license details.
   2
   3 #include "disasm.h"
   4 #include <string>
   5 #include <vector>
   6 #include <cstdarg>
   7 #include <sstream>
   8 #include <stdlib.h>
   9
  10 static const char* xpr[] = {
  11   "zero", "ra", "s0", "s1",  "s2",  "s3",  "s4",  "s5",
  12   "s6",   "s7", "s8", "s9", "s10", "s11",  "sp",  "tp",
  13   "v0",   "v1", "a0", "a1",  "a2",  "a3",  "a4",  "a5",
  14   "a6",   "a7", "t0", "t1",  "t2",  "t3",  "t4",  "gp"
  15 };
  16
  17 static const char* fpr[] = {
  18   "fs0", "fs1",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7",
  19   "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
  20   "fv0", "fv1", "fa0",   "fa1",  "fa2",  "fa3",  "fa4",  "fa5",
  21   "fa6", "fa7", "ft0",   "ft1",  "ft2",  "ft3",  "ft4",  "ft5"
  22 };
  23
  24 struct : public arg_t {
  25   std::string to_string(insn_t insn) const {
  26     return std::to_string((int)insn.i_imm()) + '(' + xpr[insn.rs1()] + ')';
  27   }
  28 } load_address;
  29
  30 struct : public arg_t {
  31   std::string to_string(insn_t insn) const {
  32     return std::to_string((int)insn.s_imm()) + '(' + xpr[insn.rs1()] + ')';
  33   }
  34 } store_address;
  35
  36 struct : public arg_t {
  37   std::string to_string(insn_t insn) const {
  38     return std::string("0(") + xpr[insn.rs1()] + ')';
  39   }
  40 } amo_address;
  41
  42 struct : public arg_t {
  43   std::string to_string(insn_t insn) const {
  44     return xpr[insn.rd()];
  45   }
  46 } xrd;
  47
  48 struct : public arg_t {
  49   std::string to_string(insn_t insn) const {
  50     return xpr[insn.rs1()];
  51   }
  52 } xrs1;
  53
  54 struct : public arg_t {
  55   std::string to_string(insn_t insn) const {
  56     return xpr[insn.rs2()];
  57   }
  58 } xrs2;
  59
  60 struct : public arg_t {
  61   std::string to_string(insn_t insn) const {
  62     return fpr[insn.rd()];
  63   }
  64 } frd;
  65
  66 struct : public arg_t {
  67   std::string to_string(insn_t insn) const {
  68     return fpr[insn.rs1()];
  69   }
  70 } frs1;
  71
  72 struct : public arg_t {
  73   std::string to_string(insn_t insn) const {
  74     return fpr[insn.rs2()];
  75   }
  76 } frs2;
  77
  78 struct : public arg_t {
  79   std::string to_string(insn_t insn) const {
  80     return fpr[insn.rs3()];
  81   }
  82 } frs3;
  83
  84 struct : public arg_t {
  85   std::string to_string(insn_t insn) const {
  86     switch (insn.csr())
  87     {
  88       #define DECLARE_CSR(name, num) case num: return #name;
  89       #include "encoding.h"
  90       #undef DECLARE_CSR
  91       default: return "unknown";
  92     }
  93   }
  94 } csr;
  95
  96 struct : public arg_t {
  97   std::string to_string(insn_t insn) const {
  98     return std::to_string((int)insn.i_imm());
  99   }
 100 } imm;
 101
 102 struct : public arg_t {
 103   std::string to_string(insn_t insn) const {
 104     std::stringstream s;
 105     s << std::hex << "0x" << ((uint32_t)insn.u_imm() >> 12);
 106     return s.str();
 107   }
 108 } bigimm;
 109
 110 struct : public arg_t {
 111   std::string to_string(insn_t insn) const {
 112     return std::to_string(insn.rs1());
 113   }
 114 } zimm5;
 115
 116 struct : public arg_t {
 117   std::string to_string(insn_t insn) const {
 118     std::stringstream s;
 119     int32_t target = insn.sb_imm();
 120     char sign = target >= 0 ? '+' : '-';
 121     s << "pc " << sign << ' ' << abs(target);
 122     return s.str();
 123   }
 124 } branch_target;
 125
 126 struct : public arg_t {
 127   std::string to_string(insn_t insn) const {
 128     std::stringstream s;
 129     int32_t target = insn.sb_imm();
 130     char sign = target >= 0 ? '+' : '-';
 131     s << "pc " << sign << std::hex << " 0x" << abs(target);
 132     return s.str();
 133   }
 134 } jump_target;
 135
 136 std::string disassembler_t::disassemble(insn_t insn)
 137 {
 138   const disasm_insn_t* disasm_insn = lookup(insn);
 139   return disasm_insn ? disasm_insn->to_string(insn) : "unknown";
 140 }
 141
 142 disassembler_t::disassembler_t()
 143 {
 144   const uint32_t mask_rd = 0x1fUL << 7;
 145   const uint32_t match_rd_ra = 1UL << 7;
 146   const uint32_t mask_rs1 = 0x1fUL << 15;
 147   const uint32_t match_rs1_ra = 1UL << 15;
 148   const uint32_t mask_rs2 = 0x1fUL << 15;
 149   const uint32_t mask_imm = 0xfffUL << 20;
 150
 151   #define DECLARE_INSN(code, match, mask) \
 152    const uint32_t match_##code = match; \
 153    const uint32_t mask_##code = mask;
 154   #include "encoding.h"
 155   #undef DECLARE_INSN
 156
 157   // explicit per-instruction disassembly
 158   #define DISASM_INSN(name, code, extra, ...) \
 159     add_insn(new disasm_insn_t(name, match_##code, mask_##code | (extra), __VA_ARGS__));
 160   #define DEFINE_NOARG(code) \
 161     add_insn(new disasm_insn_t(#code, match_##code, mask_##code, {}));
 162   #define DEFINE_RTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs1, &xrs2})
 163   #define DEFINE_ITYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs1, &imm})
 164   #define DEFINE_I0TYPE(name, code) DISASM_INSN(name, code, mask_rs1, {&xrd, &imm})
 165   #define DEFINE_I1TYPE(name, code) DISASM_INSN(name, code, mask_imm, {&xrd, &xrs1})
 166   #define DEFINE_I2TYPE(name, code) DISASM_INSN(name, code, mask_rd | mask_imm, {&xrs1})
 167   #define DEFINE_LTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &bigimm})
 168   #define DEFINE_BTYPE(code) DISASM_INSN(#code, code, 0, {&xrs1, &xrs2, &branch_target})
 169   #define DEFINE_B0TYPE(name, code) DISASM_INSN(name, code, mask_rs1 | mask_rs2, {&branch_target})
 170   #define DEFINE_B1TYPE(name, code) DISASM_INSN(name, code, mask_rs2, {&xrs1, &branch_target})
 171   #define DEFINE_XLOAD(code) DISASM_INSN(#code, code, 0, {&xrd, &load_address})
 172   #define DEFINE_XSTORE(code) DISASM_INSN(#code, code, 0, {&xrs2, &store_address})
 173   #define DEFINE_XAMO(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs2, &amo_address})
 174   #define DEFINE_FLOAD(code) DISASM_INSN(#code, code, 0, {&frd, &load_address})
 175   #define DEFINE_FSTORE(code) DISASM_INSN(#code, code, 0, {&frs2, &store_address})
 176   #define DEFINE_FRTYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1, &frs2})
 177   #define DEFINE_FR1TYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1})
 178   #define DEFINE_FR3TYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1, &frs2, &frs3})
 179   #define DEFINE_FXTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &frs1})
 180   #define DEFINE_XFTYPE(code) DISASM_INSN(#code, code, 0, {&frd, &xrs1})
 181
 182   DEFINE_XLOAD(lb)
 183   DEFINE_XLOAD(lbu)
 184   DEFINE_XLOAD(lh)
 185   DEFINE_XLOAD(lhu)
 186   DEFINE_XLOAD(lw)
 187   DEFINE_XLOAD(lwu)
 188   DEFINE_XLOAD(ld)
 189
 190   DEFINE_XSTORE(sb)
 191   DEFINE_XSTORE(sh)
 192   DEFINE_XSTORE(sw)
 193   DEFINE_XSTORE(sd)
 194
 195   DEFINE_XAMO(amoadd_w)
 196   DEFINE_XAMO(amoswap_w)
 197   DEFINE_XAMO(amoand_w)
 198   DEFINE_XAMO(amoor_w)
 199   DEFINE_XAMO(amoxor_w)
 200   DEFINE_XAMO(amomin_w)
 201   DEFINE_XAMO(amomax_w)
 202   DEFINE_XAMO(amominu_w)
 203   DEFINE_XAMO(amomaxu_w)
 204   DEFINE_XAMO(amoadd_d)
 205   DEFINE_XAMO(amoswap_d)
 206   DEFINE_XAMO(amoand_d)
 207   DEFINE_XAMO(amoor_d)
 208   DEFINE_XAMO(amoxor_d)
 209   DEFINE_XAMO(amomin_d)
 210   DEFINE_XAMO(amomax_d)
 211   DEFINE_XAMO(amominu_d)
 212   DEFINE_XAMO(amomaxu_d)
 213
 214   DEFINE_XAMO(lr_w)
 215   DEFINE_XAMO(sc_w)
 216   DEFINE_XAMO(lr_d)
 217   DEFINE_XAMO(sc_d)
 218
 219   DEFINE_FLOAD(flw)
 220   DEFINE_FLOAD(fld)
 221
 222   DEFINE_FSTORE(fsw)
 223   DEFINE_FSTORE(fsd)
 224
 225   add_insn(new disasm_insn_t("j", match_jal, mask_jal | mask_rd, {&jump_target}));
 226   add_insn(new disasm_insn_t("jal", match_jal | match_rd_ra, mask_jal | mask_rd, {&jump_target}));
 227   add_insn(new disasm_insn_t("jal", match_jal, mask_jal, {&xrd, &jump_target}));
 228
 229   DEFINE_B0TYPE("b",    beq);
 230   DEFINE_B1TYPE("beqz", beq);
 231   DEFINE_B1TYPE("bnez", bne);
 232   DEFINE_B1TYPE("bltz", blt);
 233   DEFINE_B1TYPE("bgez", bge);
 234   DEFINE_BTYPE(beq)
 235   DEFINE_BTYPE(bne)
 236   DEFINE_BTYPE(blt)
 237   DEFINE_BTYPE(bge)
 238   DEFINE_BTYPE(bltu)
 239   DEFINE_BTYPE(bgeu)
 240
 241   DEFINE_LTYPE(lui);
 242   DEFINE_LTYPE(auipc);
 243
 244   DEFINE_I2TYPE("jr", jalr);
 245   add_insn(new disasm_insn_t("jalr", match_jalr | match_rd_ra, mask_jalr | mask_rd | mask_imm, {&xrs1}));
 246   add_insn(new disasm_insn_t("ret", match_jalr | match_rs1_ra, mask_jalr | mask_rd | mask_rs1 | mask_imm, {}));
 247   DEFINE_ITYPE(jalr);
 248
 249   add_insn(new disasm_insn_t("nop", match_addi, mask_addi | mask_rd | mask_rs1 | mask_imm, {}));
 250   add_insn(new disasm_insn_t(" - ", match_xor, mask_xor | mask_rd | mask_rs1 | mask_rs2, {})); // for machine-generated bubbles
 251   DEFINE_I0TYPE("li", addi);
 252   DEFINE_I1TYPE("move", addi);
 253   DEFINE_ITYPE(addi);
 254   DEFINE_ITYPE(slli);
 255   DEFINE_ITYPE(slti);
 256   DEFINE_ITYPE(sltiu);
 257   DEFINE_ITYPE(xori);
 258   DEFINE_ITYPE(srli);
 259   DEFINE_ITYPE(srai);
 260   DEFINE_ITYPE(ori);
 261   DEFINE_ITYPE(andi);
 262   DEFINE_ITYPE(addiw);
 263   DEFINE_ITYPE(slliw);
 264   DEFINE_ITYPE(srliw);
 265   DEFINE_ITYPE(sraiw);
 266
 267   DEFINE_RTYPE(add);
 268   DEFINE_RTYPE(sub);
 269   DEFINE_RTYPE(sll);
 270   DEFINE_RTYPE(slt);
 271   DEFINE_RTYPE(sltu);
 272   DEFINE_RTYPE(xor);
 273   DEFINE_RTYPE(srl);
 274   DEFINE_RTYPE(sra);
 275   DEFINE_RTYPE(or);
 276   DEFINE_RTYPE(and);
 277   DEFINE_RTYPE(mul);
 278   DEFINE_RTYPE(mulh);
 279   DEFINE_RTYPE(mulhu);
 280   DEFINE_RTYPE(mulhsu);
 281   DEFINE_RTYPE(div);
 282   DEFINE_RTYPE(divu);
 283   DEFINE_RTYPE(rem);
 284   DEFINE_RTYPE(remu);
 285   DEFINE_RTYPE(addw);
 286   DEFINE_RTYPE(subw);
 287   DEFINE_RTYPE(sllw);
 288   DEFINE_RTYPE(srlw);
 289   DEFINE_RTYPE(sraw);
 290   DEFINE_RTYPE(mulw);
 291   DEFINE_RTYPE(divw);
 292   DEFINE_RTYPE(divuw);
 293   DEFINE_RTYPE(remw);
 294   DEFINE_RTYPE(remuw);
 295
 296   DEFINE_NOARG(scall);
 297   DEFINE_NOARG(sbreak);
 298   DEFINE_NOARG(fence);
 299   DEFINE_NOARG(fence_i);
 300
 301   add_insn(new disasm_insn_t("csrr", match_csrrs, mask_csrrs | mask_rs1, {&xrd, &csr}));
 302   add_insn(new disasm_insn_t("csrw", match_csrrw, mask_csrrw | mask_rd, {&csr, &xrs1}));
 303   add_insn(new disasm_insn_t("csrrw", match_csrrw, mask_csrrw, {&xrd, &csr, &xrs1}));
 304   add_insn(new disasm_insn_t("csrrs", match_csrrs, mask_csrrs, {&xrd, &csr, &xrs1}));
 305   add_insn(new disasm_insn_t("csrrc", match_csrrc, mask_csrrc, {&xrd, &csr, &xrs1}));
 306   add_insn(new disasm_insn_t("csrrwi", match_csrrwi, mask_csrrwi, {&xrd, &csr, &zimm5}));
 307   add_insn(new disasm_insn_t("csrrsi", match_csrrsi, mask_csrrsi, {&xrd, &csr, &zimm5}));
 308   add_insn(new disasm_insn_t("csrrci", match_csrrci, mask_csrrci, {&xrd, &csr, &zimm5}));
 309   DEFINE_NOARG(sret)
 310
 311   DEFINE_FRTYPE(fadd_s);
 312   DEFINE_FRTYPE(fsub_s);
 313   DEFINE_FRTYPE(fmul_s);
 314   DEFINE_FRTYPE(fdiv_s);
 315   DEFINE_FR1TYPE(fsqrt_s);
 316   DEFINE_FRTYPE(fmin_s);
 317   DEFINE_FRTYPE(fmax_s);
 318   DEFINE_FR3TYPE(fmadd_s);
 319   DEFINE_FR3TYPE(fmsub_s);
 320   DEFINE_FR3TYPE(fnmadd_s);
 321   DEFINE_FR3TYPE(fnmsub_s);
 322   DEFINE_FRTYPE(fsgnj_s);
 323   DEFINE_FRTYPE(fsgnjn_s);
 324   DEFINE_FRTYPE(fsgnjx_s);
 325   DEFINE_FR1TYPE(fcvt_s_d);
 326   DEFINE_XFTYPE(fcvt_s_l);
 327   DEFINE_XFTYPE(fcvt_s_lu);
 328   DEFINE_XFTYPE(fcvt_s_w);
 329   DEFINE_XFTYPE(fcvt_s_wu);
 330   DEFINE_XFTYPE(fcvt_s_wu);
 331   DEFINE_XFTYPE(fmv_s_x);
 332   DEFINE_FXTYPE(fcvt_l_s);
 333   DEFINE_FXTYPE(fcvt_lu_s);
 334   DEFINE_FXTYPE(fcvt_w_s);
 335   DEFINE_FXTYPE(fcvt_wu_s);
 336   DEFINE_FXTYPE(fmv_x_s);
 337   DEFINE_FXTYPE(feq_s);
 338   DEFINE_FXTYPE(flt_s);
 339   DEFINE_FXTYPE(fle_s);
 340
 341   DEFINE_FRTYPE(fadd_d);
 342   DEFINE_FRTYPE(fsub_d);
 343   DEFINE_FRTYPE(fmul_d);
 344   DEFINE_FRTYPE(fdiv_d);
 345   DEFINE_FR1TYPE(fsqrt_d);
 346   DEFINE_FRTYPE(fmin_d);
 347   DEFINE_FRTYPE(fmax_d);
 348   DEFINE_FR3TYPE(fmadd_d);
 349   DEFINE_FR3TYPE(fmsub_d);
 350   DEFINE_FR3TYPE(fnmadd_d);
 351   DEFINE_FR3TYPE(fnmsub_d);
 352   DEFINE_FRTYPE(fsgnj_d);
 353   DEFINE_FRTYPE(fsgnjn_d);
 354   DEFINE_FRTYPE(fsgnjx_d);
 355   DEFINE_FR1TYPE(fcvt_d_s);
 356   DEFINE_XFTYPE(fcvt_d_l);
 357   DEFINE_XFTYPE(fcvt_d_lu);
 358   DEFINE_XFTYPE(fcvt_d_w);
 359   DEFINE_XFTYPE(fcvt_d_wu);
 360   DEFINE_XFTYPE(fcvt_d_wu);
 361   DEFINE_XFTYPE(fmv_d_x);
 362   DEFINE_FXTYPE(fcvt_l_d);
 363   DEFINE_FXTYPE(fcvt_lu_d);
 364   DEFINE_FXTYPE(fcvt_w_d);
 365   DEFINE_FXTYPE(fcvt_wu_d);
 366   DEFINE_FXTYPE(fmv_x_d);
 367   DEFINE_FXTYPE(feq_d);
 368   DEFINE_FXTYPE(flt_d);
 369   DEFINE_FXTYPE(fle_d);
 370
 371   // provide a default disassembly for all instructions as a fallback
 372   #define DECLARE_INSN(code, match, mask) \
 373    add_insn(new disasm_insn_t(#code " (args unknown)", match, mask, {}));
 374   #include "encoding.h"
 375   #undef DECLARE_INSN
 376 }
 377
 378 const disasm_insn_t* disassembler_t::lookup(insn_t insn)
 379 {
 380   size_t idx = insn.bits() % HASH_SIZE;
 381   for (size_t j = 0; j < chain[idx].size(); j++)
 382     if(*chain[idx][j] == insn)
 383       return chain[idx][j];
 384
 385   idx = HASH_SIZE;
 386   for (size_t j = 0; j < chain[idx].size(); j++)
 387     if(*chain[idx][j] == insn)
 388       return chain[idx][j];
 389
 390   return NULL;
 391 }
 392
 393 void disassembler_t::add_insn(disasm_insn_t* insn)
 394 {
 395   size_t idx = HASH_SIZE;
 396   if (insn->get_mask() % HASH_SIZE == HASH_SIZE - 1)
 397     idx = insn->get_match() % HASH_SIZE;
 398   chain[idx].push_back(insn);
 399 }
 400
 401 disassembler_t::~disassembler_t()
 402 {
 403   for (size_t i = 0; i < HASH_SIZE+1; i++)
 404     for (size_t j = 0; j < chain[i].size(); j++)
 405       delete chain[i][j];
 406 }