Add some missing RVC instructions to disassembler
[riscv-isa-sim.git] / spike_main / spike.cc
1 // See LICENSE for license details.
2
3 #include "sim.h"
4 #include "mmu.h"
5 #include "remote_bitbang.h"
6 #include "cachesim.h"
7 #include "extension.h"
8 #include <dlfcn.h>
9 #include <fesvr/option_parser.h>
10 #include <stdio.h>
11 #include <stdlib.h>
12 #include <vector>
13 #include <string>
14 #include <memory>
15
16 static void help()
17 {
18 fprintf(stderr, "usage: spike [host options] <target program> [target options]\n");
19 fprintf(stderr, "Host Options:\n");
20 fprintf(stderr, " -p<n> Simulate <n> processors [default 1]\n");
21 fprintf(stderr, " -m<n> Provide <n> MiB of target memory [default 2048]\n");
22 fprintf(stderr, " -m<a:m,b:n,...> Provide memory regions of size m and n bytes\n");
23 fprintf(stderr, " at base addresses a and b (with 4 KiB alignment)\n");
24 fprintf(stderr, " -d Interactive debug mode\n");
25 fprintf(stderr, " -g Track histogram of PCs\n");
26 fprintf(stderr, " -l Generate a log of execution\n");
27 fprintf(stderr, " -h Print this help message\n");
28 fprintf(stderr, " -H Start halted, allowing a debugger to connect\n");
29 fprintf(stderr, " --isa=<name> RISC-V ISA string [default %s]\n", DEFAULT_ISA);
30 fprintf(stderr, " --pc=<address> Override ELF entry point\n");
31 fprintf(stderr, " --hartids=<a,b,...> Explicitly specify hartids, default is 0,1,...\n");
32 fprintf(stderr, " --ic=<S>:<W>:<B> Instantiate a cache model with S sets,\n");
33 fprintf(stderr, " --dc=<S>:<W>:<B> W ways, and B-byte blocks (with S and\n");
34 fprintf(stderr, " --l2=<S>:<W>:<B> B both powers of 2).\n");
35 fprintf(stderr, " --extension=<name> Specify RoCC Extension\n");
36 fprintf(stderr, " --extlib=<name> Shared library to load\n");
37 fprintf(stderr, " --rbb-port=<port> Listen on <port> for remote bitbang connection\n");
38 fprintf(stderr, " --dump-dts Print device tree string and exit\n");
39 fprintf(stderr, " --progsize=<words> progsize for the debug module [default 2]\n");
40 exit(1);
41 }
42
43 static std::vector<std::pair<reg_t, mem_t*>> make_mems(const char* arg)
44 {
45 // handle legacy mem argument
46 char* p;
47 auto mb = strtoull(arg, &p, 0);
48 if (*p == 0) {
49 reg_t size = reg_t(mb) << 20;
50 return std::vector<std::pair<reg_t, mem_t*>>(1, std::make_pair(reg_t(DRAM_BASE), new mem_t(size)));
51 }
52
53 // handle base/size tuples
54 std::vector<std::pair<reg_t, mem_t*>> res;
55 while (true) {
56 auto base = strtoull(arg, &p, 0);
57 if (!*p || *p != ':')
58 help();
59 auto size = strtoull(p + 1, &p, 0);
60 if ((size | base) % PGSIZE != 0)
61 help();
62 res.push_back(std::make_pair(reg_t(base), new mem_t(size)));
63 if (!*p)
64 break;
65 if (*p != ',')
66 help();
67 arg = p + 1;
68 }
69 return res;
70 }
71
72 int main(int argc, char** argv)
73 {
74 bool debug = false;
75 bool halted = false;
76 bool histogram = false;
77 bool log = false;
78 bool dump_dts = false;
79 size_t nprocs = 1;
80 reg_t start_pc = reg_t(-1);
81 std::vector<std::pair<reg_t, mem_t*>> mems;
82 std::unique_ptr<icache_sim_t> ic;
83 std::unique_ptr<dcache_sim_t> dc;
84 std::unique_ptr<cache_sim_t> l2;
85 std::function<extension_t*()> extension;
86 const char* isa = DEFAULT_ISA;
87 uint16_t rbb_port = 0;
88 bool use_rbb = false;
89 unsigned progsize = 2;
90 std::vector<int> hartids;
91
92 auto const hartids_parser = [&](const char *s) {
93 std::string const str(s);
94 std::stringstream stream(str);
95
96 int n;
97 while (stream >> n)
98 {
99 hartids.push_back(n);
100 if (stream.peek() == ',') stream.ignore();
101 }
102 };
103
104 option_parser_t parser;
105 parser.help(&help);
106 parser.option('h', 0, 0, [&](const char* s){help();});
107 parser.option('d', 0, 0, [&](const char* s){debug = true;});
108 parser.option('g', 0, 0, [&](const char* s){histogram = true;});
109 parser.option('l', 0, 0, [&](const char* s){log = true;});
110 parser.option('p', 0, 1, [&](const char* s){nprocs = atoi(s);});
111 parser.option('m', 0, 1, [&](const char* s){mems = make_mems(s);});
112 // I wanted to use --halted, but for some reason that doesn't work.
113 parser.option('H', 0, 0, [&](const char* s){halted = true;});
114 parser.option(0, "rbb-port", 1, [&](const char* s){use_rbb = true; rbb_port = atoi(s);});
115 parser.option(0, "pc", 1, [&](const char* s){start_pc = strtoull(s, 0, 0);});
116 parser.option(0, "hartids", 1, hartids_parser);
117 parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));});
118 parser.option(0, "dc", 1, [&](const char* s){dc.reset(new dcache_sim_t(s));});
119 parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));});
120 parser.option(0, "isa", 1, [&](const char* s){isa = s;});
121 parser.option(0, "extension", 1, [&](const char* s){extension = find_extension(s);});
122 parser.option(0, "dump-dts", 0, [&](const char *s){dump_dts = true;});
123 parser.option(0, "extlib", 1, [&](const char *s){
124 void *lib = dlopen(s, RTLD_NOW | RTLD_GLOBAL);
125 if (lib == NULL) {
126 fprintf(stderr, "Unable to load extlib '%s': %s\n", s, dlerror());
127 exit(-1);
128 }
129 });
130 parser.option(0, "progsize", 1, [&](const char* s){progsize = atoi(s);});
131
132 auto argv1 = parser.parse(argv);
133 std::vector<std::string> htif_args(argv1, (const char*const*)argv + argc);
134 if (mems.empty())
135 mems = make_mems("2048");
136
137 sim_t s(isa, nprocs, halted, start_pc, mems, htif_args, std::move(hartids),
138 progsize);
139 std::unique_ptr<remote_bitbang_t> remote_bitbang((remote_bitbang_t *) NULL);
140 std::unique_ptr<jtag_dtm_t> jtag_dtm(new jtag_dtm_t(&s.debug_module));
141 if (use_rbb) {
142 remote_bitbang.reset(new remote_bitbang_t(rbb_port, &(*jtag_dtm)));
143 s.set_remote_bitbang(&(*remote_bitbang));
144 }
145
146 if (dump_dts) {
147 printf("%s", s.get_dts());
148 return 0;
149 }
150
151 if (!*argv1)
152 help();
153
154 if (ic && l2) ic->set_miss_handler(&*l2);
155 if (dc && l2) dc->set_miss_handler(&*l2);
156 for (size_t i = 0; i < nprocs; i++)
157 {
158 if (ic) s.get_core(i)->get_mmu()->register_memtracer(&*ic);
159 if (dc) s.get_core(i)->get_mmu()->register_memtracer(&*dc);
160 if (extension) s.get_core(i)->register_extension(extension());
161 }
162
163 s.set_debug(debug);
164 s.set_log(log);
165 s.set_histogram(histogram);
166 return s.run();
167 }