Merge pull request #171 from riscv/sysbusbits
[riscv-isa-sim.git] / spike_main / spike.cc
1 // See LICENSE for license details.
2
3 #include "sim.h"
4 #include "mmu.h"
5 #include "remote_bitbang.h"
6 #include "cachesim.h"
7 #include "extension.h"
8 #include <dlfcn.h>
9 #include <fesvr/option_parser.h>
10 #include <stdio.h>
11 #include <stdlib.h>
12 #include <vector>
13 #include <string>
14 #include <memory>
15
16 static void help()
17 {
18 fprintf(stderr, "usage: spike [host options] <target program> [target options]\n");
19 fprintf(stderr, "Host Options:\n");
20 fprintf(stderr, " -p<n> Simulate <n> processors [default 1]\n");
21 fprintf(stderr, " -m<n> Provide <n> MiB of target memory [default 2048]\n");
22 fprintf(stderr, " -m<a:m,b:n,...> Provide memory regions of size m and n bytes\n");
23 fprintf(stderr, " at base addresses a and b (with 4 KiB alignment)\n");
24 fprintf(stderr, " -d Interactive debug mode\n");
25 fprintf(stderr, " -g Track histogram of PCs\n");
26 fprintf(stderr, " -l Generate a log of execution\n");
27 fprintf(stderr, " -h Print this help message\n");
28 fprintf(stderr, " -H Start halted, allowing a debugger to connect\n");
29 fprintf(stderr, " --isa=<name> RISC-V ISA string [default %s]\n", DEFAULT_ISA);
30 fprintf(stderr, " --pc=<address> Override ELF entry point\n");
31 fprintf(stderr, " --hartids=<a,b,...> Explicitly specify hartids, default is 0,1,...\n");
32 fprintf(stderr, " --ic=<S>:<W>:<B> Instantiate a cache model with S sets,\n");
33 fprintf(stderr, " --dc=<S>:<W>:<B> W ways, and B-byte blocks (with S and\n");
34 fprintf(stderr, " --l2=<S>:<W>:<B> B both powers of 2).\n");
35 fprintf(stderr, " --extension=<name> Specify RoCC Extension\n");
36 fprintf(stderr, " --extlib=<name> Shared library to load\n");
37 fprintf(stderr, " --rbb-port=<port> Listen on <port> for remote bitbang connection\n");
38 fprintf(stderr, " --dump-dts Print device tree string and exit\n");
39 fprintf(stderr, " --progsize=<words> progsize for the debug module [default 2]\n");
40 fprintf(stderr, " --debug-sba=<bits> debug bus master supports up to "
41 "<bits> wide accesses [default 0]\n");
42 exit(1);
43 }
44
45 static std::vector<std::pair<reg_t, mem_t*>> make_mems(const char* arg)
46 {
47 // handle legacy mem argument
48 char* p;
49 auto mb = strtoull(arg, &p, 0);
50 if (*p == 0) {
51 reg_t size = reg_t(mb) << 20;
52 if (size != (size_t)size)
53 throw std::runtime_error("Size would overflow size_t");
54 return std::vector<std::pair<reg_t, mem_t*>>(1, std::make_pair(reg_t(DRAM_BASE), new mem_t(size)));
55 }
56
57 // handle base/size tuples
58 std::vector<std::pair<reg_t, mem_t*>> res;
59 while (true) {
60 auto base = strtoull(arg, &p, 0);
61 if (!*p || *p != ':')
62 help();
63 auto size = strtoull(p + 1, &p, 0);
64 if ((size | base) % PGSIZE != 0)
65 help();
66 res.push_back(std::make_pair(reg_t(base), new mem_t(size)));
67 if (!*p)
68 break;
69 if (*p != ',')
70 help();
71 arg = p + 1;
72 }
73 return res;
74 }
75
76 int main(int argc, char** argv)
77 {
78 bool debug = false;
79 bool halted = false;
80 bool histogram = false;
81 bool log = false;
82 bool dump_dts = false;
83 size_t nprocs = 1;
84 reg_t start_pc = reg_t(-1);
85 std::vector<std::pair<reg_t, mem_t*>> mems;
86 std::unique_ptr<icache_sim_t> ic;
87 std::unique_ptr<dcache_sim_t> dc;
88 std::unique_ptr<cache_sim_t> l2;
89 std::function<extension_t*()> extension;
90 const char* isa = DEFAULT_ISA;
91 uint16_t rbb_port = 0;
92 bool use_rbb = false;
93 unsigned progsize = 2;
94 unsigned max_bus_master_bits = 0;
95 std::vector<int> hartids;
96
97 auto const hartids_parser = [&](const char *s) {
98 std::string const str(s);
99 std::stringstream stream(str);
100
101 int n;
102 while (stream >> n)
103 {
104 hartids.push_back(n);
105 if (stream.peek() == ',') stream.ignore();
106 }
107 };
108
109 option_parser_t parser;
110 parser.help(&help);
111 parser.option('h', 0, 0, [&](const char* s){help();});
112 parser.option('d', 0, 0, [&](const char* s){debug = true;});
113 parser.option('g', 0, 0, [&](const char* s){histogram = true;});
114 parser.option('l', 0, 0, [&](const char* s){log = true;});
115 parser.option('p', 0, 1, [&](const char* s){nprocs = atoi(s);});
116 parser.option('m', 0, 1, [&](const char* s){mems = make_mems(s);});
117 // I wanted to use --halted, but for some reason that doesn't work.
118 parser.option('H', 0, 0, [&](const char* s){halted = true;});
119 parser.option(0, "rbb-port", 1, [&](const char* s){use_rbb = true; rbb_port = atoi(s);});
120 parser.option(0, "pc", 1, [&](const char* s){start_pc = strtoull(s, 0, 0);});
121 parser.option(0, "hartids", 1, hartids_parser);
122 parser.option(0, "ic", 1, [&](const char* s){ic.reset(new icache_sim_t(s));});
123 parser.option(0, "dc", 1, [&](const char* s){dc.reset(new dcache_sim_t(s));});
124 parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));});
125 parser.option(0, "isa", 1, [&](const char* s){isa = s;});
126 parser.option(0, "extension", 1, [&](const char* s){extension = find_extension(s);});
127 parser.option(0, "dump-dts", 0, [&](const char *s){dump_dts = true;});
128 parser.option(0, "extlib", 1, [&](const char *s){
129 void *lib = dlopen(s, RTLD_NOW | RTLD_GLOBAL);
130 if (lib == NULL) {
131 fprintf(stderr, "Unable to load extlib '%s': %s\n", s, dlerror());
132 exit(-1);
133 }
134 });
135 parser.option(0, "progsize", 1, [&](const char* s){progsize = atoi(s);});
136 parser.option(0, "debug-sba", 1,
137 [&](const char* s){max_bus_master_bits = atoi(s);});
138
139 auto argv1 = parser.parse(argv);
140 std::vector<std::string> htif_args(argv1, (const char*const*)argv + argc);
141 if (mems.empty())
142 mems = make_mems("2048");
143
144 sim_t s(isa, nprocs, halted, start_pc, mems, htif_args, std::move(hartids),
145 progsize, max_bus_master_bits);
146 std::unique_ptr<remote_bitbang_t> remote_bitbang((remote_bitbang_t *) NULL);
147 std::unique_ptr<jtag_dtm_t> jtag_dtm(new jtag_dtm_t(&s.debug_module));
148 if (use_rbb) {
149 remote_bitbang.reset(new remote_bitbang_t(rbb_port, &(*jtag_dtm)));
150 s.set_remote_bitbang(&(*remote_bitbang));
151 }
152
153 if (dump_dts) {
154 printf("%s", s.get_dts());
155 return 0;
156 }
157
158 if (!*argv1)
159 help();
160
161 if (ic && l2) ic->set_miss_handler(&*l2);
162 if (dc && l2) dc->set_miss_handler(&*l2);
163 for (size_t i = 0; i < nprocs; i++)
164 {
165 if (ic) s.get_core(i)->get_mmu()->register_memtracer(&*ic);
166 if (dc) s.get_core(i)->get_mmu()->register_memtracer(&*dc);
167 if (extension) s.get_core(i)->register_extension(extension());
168 }
169
170 s.set_debug(debug);
171 s.set_log(log);
172 s.set_histogram(histogram);
173 return s.run();
174 }