Fix debug reset.
[riscv-isa-sim.git] / tests / ebreak.py
1 #!/usr/bin/python
2
3 import os
4 import testlib
5 import unittest
6 import tempfile
7 import time
8
9 class EbreakTest(unittest.TestCase):
10 def setUp(self):
11 self.binary = testlib.compile("ebreak.s")
12
13 def test_noport(self):
14 """Make sure that we can run past ebreak when --gdb-port isn't used."""
15 spike = testlib.Spike(self.binary, with_gdb=False, timeout=10)
16 result = spike.wait()
17 self.assertEqual(result, 0)
18
19 def test_nogdb(self):
20 """Make sure that we can run past ebreak when gdb isn't attached."""
21 spike = testlib.Spike(self.binary, timeout=10)
22 result = spike.wait()
23 self.assertEqual(result, 0)
24
25 if __name__ == '__main__':
26 unittest.main()