Fix for issue #183: No illegal instruction exception for c.sxxi instructions encoded...

[riscv-isa-sim.git] / riscv / insns / c_srli.h

diff --git a/riscv/insns/c_srli.h b/riscv/insns/c_srli.h
index f410fefda56322c0aa7d4d39caa2d5af3c75fbee..008ae6221e89985b2f3a0aef5c74e698137a9114 100644 (file)
--- a/riscv/insns/c_srli.h
+++ b/riscv/insns/c_srli.h
@@ -1,3 +1,3 @@
 require_extension('C');
-require(insn.rvc_zimm() < xlen);
+require(insn.rvc_zimm() < xlen && insn.rvc_zimm() > 0);
 WRITE_RVC_RS1S(sext_xlen(zext_xlen(RVC_RS1S) >> insn.rvc_zimm()));