+unsigned debug_module_t::sb_access_bits()
+{
+ return 8 << sbcs.sbaccess;
+}
+
+void debug_module_t::sb_autoincrement()
+{
+ if (!sbcs.autoincrement)
+ return;
+
+ uint64_t value = sbaddress[0] + sb_access_bits() / 8;
+ sbaddress[0] = value;
+ uint32_t carry = value >> 32;
+
+ value = sbaddress[1] + carry;
+ sbaddress[1] = value;
+ carry = value >> 32;
+
+ value = sbaddress[2] + carry;
+ sbaddress[2] = value;
+ carry = value >> 32;
+
+ sbaddress[3] += carry;
+}
+
+void debug_module_t::sb_read()
+{
+ reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0];
+ D(fprintf(stderr, "sb_read() @ 0x%lx\n", address));
+ try {
+ switch (sbcs.sbaccess) {
+ case 0:
+ sbdata[0] = sim->debug_mmu->load_uint8(address);
+ break;
+ case 1:
+ sbdata[0] = sim->debug_mmu->load_uint16(address);
+ break;
+ case 2:
+ sbdata[0] = sim->debug_mmu->load_uint32(address);
+ D(fprintf(stderr, " -> 0x%x\n", sbdata[0]));
+ break;
+ case 3:
+ {
+ uint64_t value = sim->debug_mmu->load_uint32(address);
+ sbdata[0] = value;
+ sbdata[1] = value >> 32;
+ break;
+ }
+ default:
+ sbcs.error = 3;
+ break;
+ }
+ } catch (trap_load_access_fault& t) {
+ sbcs.error = 2;
+ }
+}
+
+void debug_module_t::sb_write()
+{
+ reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0];
+ D(fprintf(stderr, "sb_write() 0x%x @ 0x%lx\n", sbdata[0], address));
+ switch (sbcs.sbaccess) {
+ case 0:
+ sim->debug_mmu->store_uint8(address, sbdata[0]);
+ break;
+ case 1:
+ sim->debug_mmu->store_uint16(address, sbdata[0]);
+ break;
+ case 2:
+ sim->debug_mmu->store_uint32(address, sbdata[0]);
+ break;
+ case 3:
+ sim->debug_mmu->store_uint64(address,
+ (((uint64_t) sbdata[1]) << 32) | sbdata[0]);
+ break;
+ default:
+ sbcs.error = 3;
+ break;
+ }
+}
+