Added commit logging (--enable-commitlog). Also fixed disasm bug.
[riscv-isa-sim.git] / riscv / disasm.cc
2013-09-27 Christopher CelioAdded commit logging (--enable-commitlog). Also fixed...
2013-09-11 Andrew WatermanImplement zany immediates
2013-09-10 Andrew WatermanAdd rd field to JAL; drop J
2013-08-08 Andrew WatermanRename MTFSR/MFFSR to FSSR/FRSR
2013-07-27 Andrew WatermanRename MFTX/MXTF to FMV
2013-07-26 Andrew WatermanRip out Hwacha for now
2013-07-26 Andrew WatermanGenerate instruction decoder dynamically
2013-07-25 Andrew WatermanRemove JALR static hints
2013-04-20 Andrew Watermanupdate abi register names
2013-04-17 Andrew Watermanadd AUIPC insn; remove RDNPC insn
2013-03-30 Andrew Watermanadd load-reserved/store-conditional instructions
2013-03-26 Andrew Watermanadd BSD license
2013-01-26 Andrew Watermanchange htif to link against libfesvr
2012-03-24 Andrew Watermannew supervisor mode
2012-03-24 Yunsup Leeadd disasm functions for vector
2012-02-13 Andrew Watermanfix sltu disassembly
2012-01-12 Andrew Watermanfix compilation for gcc 4.6.1
2011-12-11 Yunsup Leefix the fpr abi names
2011-11-12 Your NameRemove dependence on binutils