Remove MTIME[CMP]; add RTC device
[riscv-isa-sim.git] / riscv / encoding.h
2016-04-28 Andrew WatermanRemove MTIME[CMP]; add RTC device
2016-04-20 Andrew WatermanSplit ERET into URET, SRET, HRET, MRET
2016-04-06 Andrew WatermanRemove non-standard uarch CSRs
2016-03-04 Andrew WatermanFix up interrupt delegation
2016-03-02 Andrew WatermanAdd counter-enable registers
2016-03-02 Andrew WatermanWIP on priv spec v1.9
2016-03-02 Andrew WatermanNew definitions of misa/marchid/mvendorid
2016-03-02 Andrew Watermanimplement PUM functionality
2016-03-02 Andrew WatermanUse simpler MTVEC scheme
2016-03-02 Andrew WatermanWIP on priv spec v1.9
2015-11-13 Andrew WatermanGenerate device tree for target machine
2015-10-20 Andrew WatermanUpdate to hopefully final RVC 1.9 encoding
2015-10-06 Andrew WatermanRVC encoding tweak
2015-10-06 Andrew Watermanmore work towards RVC 1.8
2015-10-02 Andrew Watermanwork towards rvc 1.8
2015-09-09 Andrew WatermanImprove instruction fetch
2015-09-04 Andrew WatermanMove towards RVC v1.8
2015-09-02 Andrew WatermanDon't automatically run autoconf
2015-07-05 Andrew WatermanNew machine-mode timer facility
2015-06-01 Andrew WatermanAdd rest of RV32C instructions
2015-06-01 Andrew WatermanNew RV64C proposal
2015-05-15 Andrew WatermanMerge pull request #20 from palmer-dabbelt/package
2015-05-14 Andrew WatermanFix VM, MIP encoding
2015-05-09 Andrew WatermanUpgrade to privileged architecture 1.7
2015-04-04 Andrew WatermanSupport setting ISA/subsets with --isa flag
2015-03-31 Andrew WatermanImplement RVC draft
2015-03-27 Andrew WatermanNew virtual memory implementation (Sv39)
2015-03-17 Andrew WatermanMerge [shm]call into ecall, [shm]ret into eret
2015-03-13 Andrew WatermanUse hcall instead of mcall
2015-03-13 Andrew WatermanImplement PTE referenced/dirty bits
2015-03-13 Andrew WatermanUpdate to new privileged spec
2014-11-22 Yunsup LeeRevert "Enable support for the four custom instructions"
2014-10-24 Yunsup LeeMerge pull request #4 from arunthomas/custom_inst
2014-10-23 Arun ThomasEnable support for the four custom instructions
2014-04-03 Stephen TwiggMerge branch 'tm'
2014-04-03 Stephen TwiggSync encoding in opcodes
2014-03-18 Andrew WatermanSupport RV32 RDTIMEH/RDCYCLEH/RDINSTRETH
2014-03-12 Andrew WatermanNew FP encoding
2014-03-07 Andrew WatermanAdd fclass.{s|d} instructions
2014-02-15 Andrew WatermanRenumber uarch CSRs into custom CSR space
2014-02-06 Yunsup Leecommit missing definitions for uarch counters
2014-01-22 Andrew WatermanUse auto-generated trap cause numbers
2014-01-21 Quan NguyenMerge branch 'confprec'
2014-01-14 Andrew WatermanImprove performance for branchy code
2013-12-09 Andrew WatermanNew RDCYCLE encoding
2013-11-25 Andrew WatermanUpdate to new privileged ISA