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Set tval to 0 on traps with no specified tval
[riscv-isa-sim.git]
/
riscv
/
extension.cc
2017-05-17
Palmer Dabbelt
Merge remote-tracking branch 'origin/priv-1.10'
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2017-04-17
Megan Wachs
Merge remote-tracking branch 'origin/priv-1.10' into...
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2017-03-28
Andrew Waterman
Set badaddr=0 on illegal instruction traps
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2017-02-07
Tim Newsome
Merge pull request #83 from bacam/gdb-protocol-fixes
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2017-02-03
Andrew Waterman
Fix interrupt delegation for coprocessors
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2016-03-02
Andrew Waterman
WIP on priv spec v1.9
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2015-09-08
Andrew Waterman
Refer to LICENSE in some newer source files
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2015-03-16
Yunsup Lee
bugfix in raising accelerator interrupts
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2015-03-13
Andrew Waterman
Update to new privileged spec
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2014-01-28
Andrew Waterman
Force extension loaders to be linked in
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2014-01-27
Andrew Waterman
Eliminate hwacha <-> riscv circular dependence
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2013-10-16
Yunsup Lee
revamp hwacha; now runs in physical mode
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2013-08-13
Andrew Waterman
Implement RoCC and add a dummy RoCC
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