Set badaddr=0 on illegal instruction traps

diff --git a/riscv/decode.h b/riscv/decode.h
index 061b5b6249271152537fc2a4d299e17b5523c8a0..bec548aeb835e187473b1b1d28991536d278391d 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -174,13 +174,13 @@ private:
 #define JUMP_TARGET (pc + insn.uj_imm())
 #define RM ({ int rm = insn.rm(); \
               if(rm == 7) rm = STATE.frm; \
-              if(rm > 4) throw trap_illegal_instruction(); \
+              if(rm > 4) throw trap_illegal_instruction(0); \
               rm; })
 
 #define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1)))
 #define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask)))
 
-#define require(x) if (unlikely(!(x))) throw trap_illegal_instruction()
+#define require(x) if (unlikely(!(x))) throw trap_illegal_instruction(0)
 #define require_privilege(p) require(STATE.prv >= (p))
 #define require_rv64 require(xlen == 64)
 #define require_rv32 require(xlen == 32)
@@ -227,7 +227,7 @@ private:
   unsigned csr_priv = get_field((which), 0x300); \
   unsigned csr_read_only = get_field((which), 0xC00) == 3; \
   if (((write) && csr_read_only) || STATE.prv < csr_priv) \
-    throw trap_illegal_instruction(); \
+    throw trap_illegal_instruction(0); \
   (which); })
 
 #define DEBUG_START             0x100

diff --git a/riscv/extension.cc b/riscv/extension.cc
index a34dd8040ced3a7f97f4e3f8deac64f9529f982e..520c2ed578c3964c4cfba8c9f7da394a48c1bc5d 100644 (file)
--- a/riscv/extension.cc
+++ b/riscv/extension.cc
@@ -9,7 +9,7 @@ extension_t::~extension_t()
 
 void extension_t::illegal_instruction()
 {
-  throw trap_illegal_instruction();
+  throw trap_illegal_instruction(0);
 }
 
 void extension_t::raise_interrupt()

diff --git a/riscv/processor.cc b/riscv/processor.cc
index f6b4cb649f0c357c98b2444842a2536031145ba3..3830b1e9c65600195d35a9e39151a7b074c31bd6 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -604,12 +604,12 @@ reg_t processor_t::get_csr(int which)
     case CSR_DSCRATCH:
       return state.dscratch;
   }
-  throw trap_illegal_instruction();
+  throw trap_illegal_instruction(0);
 }
 
 reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc)
 {
-  throw trap_illegal_instruction();
+  throw trap_illegal_instruction(0);
 }
 
 insn_func_t processor_t::decode_insn(insn_t insn)

diff --git a/riscv/trap.h b/riscv/trap.h
index 20313e99c75c5a0f9b42e9f44468378d912d8fde..91e522396b42d9887372897ed19fe30252672c4a 100644 (file)
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -46,7 +46,7 @@ class mem_trap_t : public trap_t
 
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault)
-DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)
+DECLARE_MEM_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)
 DECLARE_MEM_TRAP(CAUSE_BREAKPOINT, breakpoint)
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned)