Set badaddr=0 on illegal instruction traps
[riscv-isa-sim.git] / riscv / trap.h
2017-03-28 Andrew WatermanSet badaddr=0 on illegal instruction traps
2017-03-28 Andrew WatermanOn EBREAK, set badaddr to pc
2017-03-27 Andrew WatermanSeparate page faults from physical memory access exceptions
2016-03-02 Andrew WatermanWIP on priv spec v1.9
2015-05-09 Andrew WatermanUpgrade to privileged architecture 1.7
2015-03-17 Andrew WatermanMerge [shm]call into ecall, [shm]ret into eret
2015-03-13 Andrew WatermanUse hcall instead of mcall
2015-03-13 Andrew WatermanUpdate to new privileged spec
2014-12-05 Andrew WatermanSet badvaddr on instruction page faults
2014-08-26 Scott Beamerclean up warnings from clang
2014-01-22 Andrew WatermanUse auto-generated trap cause numbers
2013-11-25 Quan NguyenMerge branch 'master' of github.com:ucb-bar/riscv-isa...
2013-11-06 Yunsup Leecorrectly trap when SR_EA is disabled
2013-10-18 Yunsup Leeadd hwacha exception support
2013-08-12 Andrew WatermanInstructions are no longer member functions
2013-03-26 Andrew Watermanadd BSD license
2012-03-24 Andrew Watermannew supervisor mode
2011-11-11 Andrew WatermanChanged supervisor mode
2011-06-20 Andrew Watermantemporary undoing of renaming
2011-06-13 Andrew Waterman[sim] renamed to riscv-isa-run
2011-05-29 Andrew Waterman[fesvr,xcc,sim] fixed multicore sim for akaros
2011-05-18 Yunsup Lee[opcodes,pk,sim] add more vector traps (for #banks...
2011-04-12 Andrew Waterman[sim,pk] fixed minor pk bugs and trap codes
2011-04-10 Yunsup Lee[sim] add vector traps to vector instructions
2011-04-10 Andrew Waterman[sim,pk] reorganized status register
2011-03-25 Andrew Waterman[xcc,pk,opcodes,sim] updated encoding/insn names
2011-02-05 Andrew Waterman[sim,pk] added interrupt-pending field to cause reg
2010-09-11 Andrew Waterman[sim, pk] cleaned up exception vectors and FP exc flags
2010-08-05 Andrew Waterman[xcc,pk,sim] Added first part of FP support
2010-07-19 Andrew WatermanReorganized directory structure