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[xcc] minor performance tweaks
[riscv-isa-sim.git]
/
riscv
/
insns
/
addiw.h
2011-01-19
Andrew Waterman
[opcodes, sim, xcc] made *w insns illegal in RV32
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2010-11-22
Andrew Waterman
[xcc, sim, pk, opcodes] new instruction encoding!
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2010-09-21
Andrew Waterman
[xcc, sim] changed instruction format so imm12 subs...
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2010-08-04
Andrew Waterman
[pk,sim,xcc] Renamed instructions to RISC-V spec
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projects / riscv-isa-sim.git / history