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Implement RVC draft
[riscv-isa-sim.git]
/
riscv
/
insns
/
slli.h
2015-03-31
Andrew Waterman
Implement RVC draft
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2015-03-13
Andrew Waterman
Update to new privileged spec
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2013-09-27
Andrew Waterman
Use WRITE_RD/WRITE_FRD macros to write registers
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2013-08-12
Andrew Waterman
Instructions are no longer member functions
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2011-06-20
Andrew Waterman
temporary undoing of renaming
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2011-06-13
Andrew Waterman
[sim] renamed to riscv-isa-run
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2011-01-19
Andrew Waterman
[opcodes, sim, xcc] made *w insns illegal in RV32
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2010-11-22
Andrew Waterman
[xcc, sim, pk, opcodes] new instruction encoding!
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2010-09-21
Andrew Waterman
[xcc, sim] changed instruction format so imm12 subs...
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2010-09-13
Andrew Waterman
[xcc, sim] moved shamt field and renamed shifts
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projects / riscv-isa-sim.git / history