git.libre-soc.org Git - riscv-isa-sim.git/history

2011-04-19	Andrew Waterman	[xcc,sim] rv64 'w' instruction semantics changed	blob \| commitdiff \| raw
2011-01-19	Andrew Waterman	[opcodes, sim, xcc] made *w insns illegal in RV32	blob \| commitdiff \| raw \| diff to current
2010-11-22	Andrew Waterman	[xcc, sim, pk, opcodes] new instruction encoding!	blob \| commitdiff \| raw \| diff to current
2010-09-21	Andrew Waterman	[xcc, sim] changed instruction format so imm12 subs...	blob \| commitdiff \| raw \| diff to current
2010-09-13	Andrew Waterman	[xcc, sim] moved shamt field and renamed shifts	blob \| commitdiff \| raw \| diff to current

Simple-V augmented version of spike