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Implement mstatus.TW, mstatus.TVM, and mstatus.TSR
[riscv-isa-sim.git]
/
riscv
/
insns
/
sret.h
2017-03-13
Andrew Waterman
Implement mstatus.TW, mstatus.TVM, and mstatus.TSR
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2017-02-07
Tim Newsome
Merge pull request #83 from bacam/gdb-protocol-fixes
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2017-02-02
Andrew Waterman
Set xPIE=1 on xRET
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2016-05-23
Tim Newsome
Add dret.
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2016-05-23
Tim Newsome
Properly save/restore dpc, mcause, mbadaddr.
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2016-04-20
Andrew Waterman
Split ERET into URET, SRET, HRET, MRET
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2016-03-02
Andrew Waterman
Fix ERET bug
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2016-03-02
Andrew Waterman
Serialize simulator on ERET
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2016-03-02
Andrew Waterman
WIP on priv spec v1.9
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2015-03-17
Andrew Waterman
Merge [shm]call into ecall, [shm]ret into eret
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2015-03-13
Andrew Waterman
Update to new privileged spec
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2014-01-21
Quan Nguyen
Merge branch 'confprec'
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2013-11-25
Andrew Waterman
Update to new privileged ISA
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