reorganise twin-predication
[riscv-isa-sim.git] / riscv / sv_decode.h
2018-10-04 Luke Kenneth Casso... reorganise twin-predication
2018-10-04 Luke Kenneth Casso... big reorganisation to support twin-predication
2018-10-03 Luke Kenneth Casso... decided not to change the behaviour of LOAD/STORE
2018-10-02 Luke Kenneth Casso... start work on parallelsing LOAD, pass in parameter...
2018-10-01 Luke Kenneth Casso... whoops vloop continuation logic the wrong way round
2018-09-30 Luke Kenneth Casso... add sv support for zeroing predication in dest register
2018-09-30 Luke Kenneth Casso... add in predication to sv instruction execution
2018-09-30 Luke Kenneth Casso... start linking in predication into sv
2018-09-30 Luke Kenneth Casso... use an alternative logic for detecting scalar / loop-end
2018-09-29 Luke Kenneth Casso... add sv_insn_t overloads for rvc registers
2018-09-29 Luke Kenneth Casso... also arrange for id_regs.py to identify compressed...
2018-09-29 Luke Kenneth Casso... reorganise from moving sv_pred_* and sv_reg_* tables...
2018-09-27 Luke Kenneth Casso... add sv predication function
2018-09-26 Luke Kenneth Casso... cache the sv redirected register values on each loop
2018-09-26 Luke Kenneth Casso... remembered that the use of sv registers have to be...
2018-09-26 Luke Kenneth Casso... ok this is tricky: an extra parameter has to be passed...
2018-09-26 Luke Kenneth Casso... move sv remap function to sv.cc (not inline)
2018-09-25 Luke Kenneth Casso... rename sv vlen to sv voffs, add csr and reg tables
2018-09-25 Luke Kenneth Casso... add reference to vector length in sv
2018-09-25 Luke Kenneth Casso... use sv_insn_t class in instruction template
2018-09-25 Luke Kenneth Casso... add sv_insn_t class (inherits from insn_t)