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debug: checkpoint of trying to get simulation tests working
author
Megan Wachs
<megan@sifive.com>
Fri, 14 Apr 2017 17:24:32 +0000
(10:24 -0700)
committer
Megan Wachs
<megan@sifive.com>
Fri, 14 Apr 2017 17:24:32 +0000
(10:24 -0700)
debug/programs/entry.S
patch
|
blob
|
history
debug/programs/mprv.S
patch
|
blob
|
history
debug/targets/HiFive1/openocd.cfg
patch
|
blob
|
history
debug/targets/freedom-e300-sim/openocd.cfg
patch
|
blob
|
history
debug/targets/freedom-e300/openocd.cfg
patch
|
blob
|
history
debug/targets/freedom-u500-sim/openocd.cfg
patch
|
blob
|
history
debug/targets/freedom-u500/openocd.cfg
patch
|
blob
|
history
debug/testlib.py
patch
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blob
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history
diff --git
a/debug/programs/entry.S
b/debug/programs/entry.S
index e021860f58c38b85b703e6992aa6488f01e7aaed..c9e319ccc0549b31d4ef148bfc2ca8c62e15556d 100755
(executable)
--- a/
debug/programs/entry.S
+++ b/
debug/programs/entry.S
@@
-30,8
+30,23
@@
handle_reset:
la t0, trap_entry
csrw mtvec, t0
csrwi mstatus, 0
la t0, trap_entry
csrw mtvec, t0
csrwi mstatus, 0
+
+ // make sure these registers exist by seeing if either S or U bits
+ // are set before attempting to zero them out.
+ csrr t1, misa
+ addi t2, x0, 1
+ slli t2, t2, 20 // U_EXTENSION
+ and t2, t1, t2
+ bne x0, t2, 1f
+ addi t2, x0, 1
+ slli t2, t2, 18 // S_EXTENSION
+ and t2, t1, t2
+ bne x0, t2, 1f
+ j 2f
+1:
csrwi mideleg, 0
csrwi medeleg, 0
csrwi mideleg, 0
csrwi medeleg, 0
+2:
csrwi mie, 0
# initialize global pointer
csrwi mie, 0
# initialize global pointer
diff --git
a/debug/programs/mprv.S
b/debug/programs/mprv.S
index 574f32e62a562a69732dd74af4903f6bf6baa841..cc1ca54b5da24216ea2137f3831a2ef942c0a3d4 100644
(file)
--- a/
debug/programs/mprv.S
+++ b/
debug/programs/mprv.S
@@
-13,9
+13,9
@@
main:
# update mstatus
csrr t1, CSR_MSTATUS
#if XLEN == 32
# update mstatus
csrr t1, CSR_MSTATUS
#if XLEN == 32
- li t0, (MSTATUS_MPRV | (
VM
_SV32 << 24))
+ li t0, (MSTATUS_MPRV | (
SPTBR_MODE
_SV32 << 24))
#else
#else
- li t0, (MSTATUS_MPRV | (
VM
_SV39 << 24))
+ li t0, (MSTATUS_MPRV | (
SPTBR_MODE
_SV39 << 24))
#endif
#li t0, ((VM_SV39 << 24))
or t1, t0, t1
#endif
#li t0, ((VM_SV39 << 24))
or t1, t0, t1
diff --git
a/debug/targets/HiFive1/openocd.cfg
b/debug/targets/HiFive1/openocd.cfg
index d2c2879358598def797d7766d3c581c655796f3c..72a54469d8664b936337d62c8b9eb9ff642d84ab 100644
(file)
--- a/
debug/targets/HiFive1/openocd.cfg
+++ b/
debug/targets/HiFive1/openocd.cfg
@@
-14,7
+14,7
@@
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
-rtos riscv
flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
init
flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
init
diff --git
a/debug/targets/freedom-e300-sim/openocd.cfg
b/debug/targets/freedom-e300-sim/openocd.cfg
index f3d9cb43a596f8fd90263d0cfaebff33da5c2903..fcb8451daa505982eab588e9196b2cc118aecb26 100644
(file)
--- a/
debug/targets/freedom-e300-sim/openocd.cfg
+++ b/
debug/targets/freedom-e300-sim/openocd.cfg
@@
-2,6
+2,7
@@
adapter_khz 10000
source [find interface/jtag_vpi.cfg]
jtag_vpi_set_port $::env(JTAG_VPI_PORT)
source [find interface/jtag_vpi.cfg]
jtag_vpi_set_port $::env(JTAG_VPI_PORT)
+#jtag_vpi_set_port 34448
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
@@
-11,3
+12,4
@@
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
init
halt
init
halt
+echo "OK GO NOW"
diff --git
a/debug/targets/freedom-e300/openocd.cfg
b/debug/targets/freedom-e300/openocd.cfg
index 0596b15cb5f31cefb2d2857493cfaa3a731150c2..5824b7724a995c180d0f156d3bf92ee00be686a8 100644
(file)
--- a/
debug/targets/freedom-e300/openocd.cfg
+++ b/
debug/targets/freedom-e300/openocd.cfg
@@
-6,7
+6,7
@@
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-rtos riscv
gdb_report_data_abort enable
gdb_report_data_abort enable
diff --git
a/debug/targets/freedom-u500-sim/openocd.cfg
b/debug/targets/freedom-u500-sim/openocd.cfg
index 9239c83ddde91c20de939040bee122b3ab03292a..0ce11d80eb4f96323b9237e99ade74a9ee223a27 100644
(file)
--- a/
debug/targets/freedom-u500-sim/openocd.cfg
+++ b/
debug/targets/freedom-u500-sim/openocd.cfg
@@
-1,8
+1,8
@@
adapter_khz 10000
source [find interface/jtag_vpi.cfg]
adapter_khz 10000
source [find interface/jtag_vpi.cfg]
-jtag_vpi_set_port $::env(JTAG_VPI_PORT)
-#jtag_vpi_set_port 44005
+
#
jtag_vpi_set_port $::env(JTAG_VPI_PORT)
+jtag_vpi_set_port 46401
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
diff --git
a/debug/targets/freedom-u500/openocd.cfg
b/debug/targets/freedom-u500/openocd.cfg
index d448989243ecc7d893ed4eca399eb2d62b737c76..3e3bcad62a9a342cbc75174a4444e1b387a6fac4 100644
(file)
--- a/
debug/targets/freedom-u500/openocd.cfg
+++ b/
debug/targets/freedom-u500/openocd.cfg
@@
-6,7
+6,7
@@
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-rtos riscv
init
init
diff --git
a/debug/testlib.py
b/debug/testlib.py
index 5a5d6e360def979992c6b567215936b600d51e25..b0a625beeb6a49fd6557ac48a59a652dec439764 100644
(file)
--- a/
debug/testlib.py
+++ b/
debug/testlib.py
@@
-19,8
+19,11
@@
def find_file(path):
return None
def compile(args, xlen=32): # pylint: disable=redefined-builtin
return None
def compile(args, xlen=32): # pylint: disable=redefined-builtin
- cc = os.path.expandvars("$RISCV/bin/riscv
%d-unknown-elf-gcc" % xlen
)
+ cc = os.path.expandvars("$RISCV/bin/riscv
64-unknown-elf-gcc"
)
cmd = [cc, "-g"]
cmd = [cc, "-g"]
+ if (xlen == 32):
+ cmd.append("-march=rv32imac")
+ cmd.append("-mabi=ilp32")
for arg in args:
found = find_file(arg)
if found:
for arg in args:
found = find_file(arg)
if found:
@@
-28,7
+31,7
@@
def compile(args, xlen=32): # pylint: disable=redefined-builtin
else:
cmd.append(arg)
process = subprocess.Popen(cmd, stdout=subprocess.PIPE,
else:
cmd.append(arg)
process = subprocess.Popen(cmd, stdout=subprocess.PIPE,
- stderr=subprocess.PIPE)
+
stderr=subprocess.PIPE)
stdout, stderr = process.communicate()
if process.returncode:
print
stdout, stderr = process.communicate()
if process.returncode:
print