Verify that mtval/stval is written correctly on misaligned fetch

diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S
index d4e5b44c4521438fcd388ef76ee11131059f7ab2..eb50f944fdbb187138ae94d23c298732b469e880 100644 (file)
--- a/isa/rv64si/ma_fetch.S
+++ b/isa/rv64si/ma_fetch.S
@@ -17,6 +17,7 @@ RVTEST_CODE_BEGIN
   #define sscratch mscratch
   #define sstatus mstatus
   #define scause mcause
   #define sscratch mscratch
   #define sstatus mstatus
   #define scause mcause

+  #define sbadaddr mbadaddr

   #define sepc mepc
   #define sret mret
   #define stvec_handler mtvec_handler
   #define sepc mepc
   #define sret mret
   #define stvec_handler mtvec_handler


@@ -132,9 +133,16 @@ stvec_handler:
 
   # verify that epc == &jalr (== t0 - 4)
   csrr a1, sepc
 
   # verify that epc == &jalr (== t0 - 4)
   csrr a1, sepc

-  addi t0, t0, -4
+  addi a1, a1, 4

   bne t0, a1, fail
 
   bne t0, a1, fail
 

+  # verify that badaddr == 0 or badaddr == t0+2.
+  csrr a0, sbadaddr
+  beqz a0, 1f
+  addi a0, a0, -2
+  bne a0, t0, fail
+1:
+

   addi a1, a1, 12
   csrw sepc, a1
   sret
   addi a1, a1, 12
   csrw sepc, a1
   sret