Makefile

   1 rv32_sim:
   2         iverilog -o rv32 -Wall cpu.v cpu_alu.v cpu_fetch_stage.v \
   3                         cpu_memory_interface.v vga*.v cpu_decoder.v \
   4         block_memory.v block_memory_16kbit.v \
   5         main.v main_test.v
   6