ReadMe.md

   1 # 32-bit RISC-V processor design
   2
   3 Implements RV32I instruction set except for interrupts and some CSRs.
   4
   5 Warning: CSR and system instructions weren't really tested so may not work properly
   6
   7 Default software runs a 2.5D maze game through the VGA port, using SW2 and SW3 to turn and move.
   8
   9 Implemented CSRs:
  10 - cycle/cycleh -- doesn't count
  11 - time/timeh -- doesn't count
  12 - instret/instreth -- doesn't count
  13 - mvendorid
  14 - marchid
  15 - mimpid
  16 - misa -- ignores writes
  17 - mstatus -- all but mpie and mie are hardwired
  18 - mie -- all but meie, mtie, and msie are hardwired
  19 - mtvec -- hardwired to 0x10040
  20 - mscratch
  21 - mepc
  22 - mcause
  23 - mip -- ignores writes
  24
  25 - used FPGA: ChinaQMTECH's QM_XC6SLX16_DDR3 board with the vga output board. [Docs](https://raw.githubusercontent.com/ChinaQMTECH/QM_XC6SLX16_DDR3/master/QM_XC6SLX16_DDR3_V02.zip) [archived on archive.org](http://web.archive.org/web/20180321000346/https://raw.githubusercontent.com/ChinaQMTECH/QM_XC6SLX16_DDR3/master/QM_XC6SLX16_DDR3_V02.zip)
  26 - used programmer: Digilent's Hs2 JTAG programmer
  27
  28 ## Building (On Ubuntu 16.04)
  29 Requires Xilinx's ISE v. 14.7 to be installed in /opt/Xilinx (just leave the default installation directory)
  30
  31     sudo apt-get install git g++ autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev
  32     sudo mkdir /opt/riscv
  33     sudo chown $USER /opt/riscv # so you don't need root when building; you can change back after building riscv-gnu-toolchain
  34     git clone --recursive https://github.com/riscv/riscv-gnu-toolchain.git
  35     export PATH=/opt/riscv/bin:"$PATH"
  36     cd riscv-gnu-toolchain
  37     ./configure --prefix=/opt/riscv --with-arch=rv32i
  38     make
  39     sudo chown -R root:root /opt/riscv # change owner back to root as the compiler is finished installing
  40     cd ..
  41     git clone https://github.com/programmerjake/rv32.git
  42     cd rv32/software
  43     make
  44     cd ..
  45     # at this point the built bitstream is in output.bit
  46     djtgcfg prog -d JtagHS2 -i 0 -f output.bit # program the FPGA
  47
  48 ## Building the hardware (only required if verilog source is modified)
  49
  50 Requires having built the software at least once to generate the ram initialization files.
  51
  52 Run `(. /opt/Xilinx/14.7/ISE_DS/settings64.sh; ise&)` in a terminal.
  53 Switch the view to Implementation
  54 Select main.v
  55 Run "Generate Programming File"
  56 Open a terminal and run:
  57
  58     export PATH=/opt/riscv/bin:"$PATH"
  59     cd rv32/software
  60     make
  61     cd ..
  62     # at this point the built bitstream is in output.bit
  63     djtgcfg prog -d JtagHS2 -i 0 -f output.bit # program the FPGA
  64