block_memory.v

   1 /*
   2  * Copyright 2018 Jacob Lifshay
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in all
  12  * copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  17  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  *
  22  */
  23 `timescale 1ns / 1ps
  24
  25 module block_memory(
  26     input clk,
  27     input [31:0] a_ram_address,
  28     input [3:0] a_write_enable,
  29     input [31:0] a_write_input,
  30     output reg [31:0] a_read_output,
  31     input [31:0] b_ram_address,
  32     output reg [31:0] b_read_output
  33     );
  34
  35     wire a_enable_0 = a_ram_address[31:11] == 0;
  36     wire b_enable_0 = b_ram_address[31:11] == 0;
  37     wire [3:0] a_write_enable_0 = {4{a_enable_0}} & a_write_enable;
  38     wire [31:0] a_read_output_0;
  39     wire [31:0] b_read_output_0;
  40     block_memory_16kbit #(
  41         .initial_file("software/ram_0_byte0.hex")
  42         ) ram_0_byte0(
  43         .clk(clk),
  44         .port_a_address(a_ram_address[10:0]),
  45         .port_a_write_enable(a_write_enable_0[0]),
  46         .port_a_write_input(a_write_input[7:0]),
  47         .port_a_read_output(a_read_output_0[7:0]),
  48         .port_b_address(b_ram_address[10:0]),
  49         .port_b_read_output(b_read_output_0[7:0])
  50         );
  51
  52     block_memory_16kbit #(
  53         .initial_file("software/ram_0_byte1.hex")
  54         ) ram_0_byte1(
  55         .clk(clk),
  56         .port_a_address(a_ram_address[10:0]),
  57         .port_a_write_enable(a_write_enable_0[1]),
  58         .port_a_write_input(a_write_input[15:8]),
  59         .port_a_read_output(a_read_output_0[15:8]),
  60         .port_b_address(b_ram_address[10:0]),
  61         .port_b_read_output(b_read_output_0[15:8])
  62         );
  63
  64     block_memory_16kbit #(
  65         .initial_file("software/ram_0_byte2.hex")
  66         ) ram_0_byte2(
  67         .clk(clk),
  68         .port_a_address(a_ram_address[10:0]),
  69         .port_a_write_enable(a_write_enable_0[2]),
  70         .port_a_write_input(a_write_input[23:16]),
  71         .port_a_read_output(a_read_output_0[23:16]),
  72         .port_b_address(b_ram_address[10:0]),
  73         .port_b_read_output(b_read_output_0[23:16])
  74         );
  75
  76     block_memory_16kbit #(
  77         .initial_file("software/ram_0_byte3.hex")
  78         ) ram_0_byte3(
  79         .clk(clk),
  80         .port_a_address(a_ram_address[10:0]),
  81         .port_a_write_enable(a_write_enable_0[3]),
  82         .port_a_write_input(a_write_input[31:24]),
  83         .port_a_read_output(a_read_output_0[31:24]),
  84         .port_b_address(b_ram_address[10:0]),
  85         .port_b_read_output(b_read_output_0[31:24])
  86         );
  87
  88
  89     wire a_enable_1 = a_ram_address[31:11] == 1;
  90     wire b_enable_1 = b_ram_address[31:11] == 1;
  91     wire [3:0] a_write_enable_1 = {4{a_enable_1}} & a_write_enable;
  92     wire [31:0] a_read_output_1;
  93     wire [31:0] b_read_output_1;
  94     block_memory_16kbit #(
  95         .initial_file("software/ram_1_byte0.hex")
  96         ) ram_1_byte0(
  97         .clk(clk),
  98         .port_a_address(a_ram_address[10:0]),
  99         .port_a_write_enable(a_write_enable_1[0]),
 100         .port_a_write_input(a_write_input[7:0]),
 101         .port_a_read_output(a_read_output_1[7:0]),
 102         .port_b_address(b_ram_address[10:0]),
 103         .port_b_read_output(b_read_output_1[7:0])
 104         );
 105
 106     block_memory_16kbit #(
 107         .initial_file("software/ram_1_byte1.hex")
 108         ) ram_1_byte1(
 109         .clk(clk),
 110         .port_a_address(a_ram_address[10:0]),
 111         .port_a_write_enable(a_write_enable_1[1]),
 112         .port_a_write_input(a_write_input[15:8]),
 113         .port_a_read_output(a_read_output_1[15:8]),
 114         .port_b_address(b_ram_address[10:0]),
 115         .port_b_read_output(b_read_output_1[15:8])
 116         );
 117
 118     block_memory_16kbit #(
 119         .initial_file("software/ram_1_byte2.hex")
 120         ) ram_1_byte2(
 121         .clk(clk),
 122         .port_a_address(a_ram_address[10:0]),
 123         .port_a_write_enable(a_write_enable_1[2]),
 124         .port_a_write_input(a_write_input[23:16]),
 125         .port_a_read_output(a_read_output_1[23:16]),
 126         .port_b_address(b_ram_address[10:0]),
 127         .port_b_read_output(b_read_output_1[23:16])
 128         );
 129
 130     block_memory_16kbit #(
 131         .initial_file("software/ram_1_byte3.hex")
 132         ) ram_1_byte3(
 133         .clk(clk),
 134         .port_a_address(a_ram_address[10:0]),
 135         .port_a_write_enable(a_write_enable_1[3]),
 136         .port_a_write_input(a_write_input[31:24]),
 137         .port_a_read_output(a_read_output_1[31:24]),
 138         .port_b_address(b_ram_address[10:0]),
 139         .port_b_read_output(b_read_output_1[31:24])
 140         );
 141
 142
 143     wire a_enable_2 = a_ram_address[31:11] == 2;
 144     wire b_enable_2 = b_ram_address[31:11] == 2;
 145     wire [3:0] a_write_enable_2 = {4{a_enable_2}} & a_write_enable;
 146     wire [31:0] a_read_output_2;
 147     wire [31:0] b_read_output_2;
 148     block_memory_16kbit #(
 149         .initial_file("software/ram_2_byte0.hex")
 150         ) ram_2_byte0(
 151         .clk(clk),
 152         .port_a_address(a_ram_address[10:0]),
 153         .port_a_write_enable(a_write_enable_2[0]),
 154         .port_a_write_input(a_write_input[7:0]),
 155         .port_a_read_output(a_read_output_2[7:0]),
 156         .port_b_address(b_ram_address[10:0]),
 157         .port_b_read_output(b_read_output_2[7:0])
 158         );
 159
 160     block_memory_16kbit #(
 161         .initial_file("software/ram_2_byte1.hex")
 162         ) ram_2_byte1(
 163         .clk(clk),
 164         .port_a_address(a_ram_address[10:0]),
 165         .port_a_write_enable(a_write_enable_2[1]),
 166         .port_a_write_input(a_write_input[15:8]),
 167         .port_a_read_output(a_read_output_2[15:8]),
 168         .port_b_address(b_ram_address[10:0]),
 169         .port_b_read_output(b_read_output_2[15:8])
 170         );
 171
 172     block_memory_16kbit #(
 173         .initial_file("software/ram_2_byte2.hex")
 174         ) ram_2_byte2(
 175         .clk(clk),
 176         .port_a_address(a_ram_address[10:0]),
 177         .port_a_write_enable(a_write_enable_2[2]),
 178         .port_a_write_input(a_write_input[23:16]),
 179         .port_a_read_output(a_read_output_2[23:16]),
 180         .port_b_address(b_ram_address[10:0]),
 181         .port_b_read_output(b_read_output_2[23:16])
 182         );
 183
 184     block_memory_16kbit #(
 185         .initial_file("software/ram_2_byte3.hex")
 186         ) ram_2_byte3(
 187         .clk(clk),
 188         .port_a_address(a_ram_address[10:0]),
 189         .port_a_write_enable(a_write_enable_2[3]),
 190         .port_a_write_input(a_write_input[31:24]),
 191         .port_a_read_output(a_read_output_2[31:24]),
 192         .port_b_address(b_ram_address[10:0]),
 193         .port_b_read_output(b_read_output_2[31:24])
 194         );
 195
 196
 197     wire a_enable_3 = a_ram_address[31:11] == 3;
 198     wire b_enable_3 = b_ram_address[31:11] == 3;
 199     wire [3:0] a_write_enable_3 = {4{a_enable_3}} & a_write_enable;
 200     wire [31:0] a_read_output_3;
 201     wire [31:0] b_read_output_3;
 202     block_memory_16kbit #(
 203         .initial_file("software/ram_3_byte0.hex")
 204         ) ram_3_byte0(
 205         .clk(clk),
 206         .port_a_address(a_ram_address[10:0]),
 207         .port_a_write_enable(a_write_enable_3[0]),
 208         .port_a_write_input(a_write_input[7:0]),
 209         .port_a_read_output(a_read_output_3[7:0]),
 210         .port_b_address(b_ram_address[10:0]),
 211         .port_b_read_output(b_read_output_3[7:0])
 212         );
 213
 214     block_memory_16kbit #(
 215         .initial_file("software/ram_3_byte1.hex")
 216         ) ram_3_byte1(
 217         .clk(clk),
 218         .port_a_address(a_ram_address[10:0]),
 219         .port_a_write_enable(a_write_enable_3[1]),
 220         .port_a_write_input(a_write_input[15:8]),
 221         .port_a_read_output(a_read_output_3[15:8]),
 222         .port_b_address(b_ram_address[10:0]),
 223         .port_b_read_output(b_read_output_3[15:8])
 224         );
 225
 226     block_memory_16kbit #(
 227         .initial_file("software/ram_3_byte2.hex")
 228         ) ram_3_byte2(
 229         .clk(clk),
 230         .port_a_address(a_ram_address[10:0]),
 231         .port_a_write_enable(a_write_enable_3[2]),
 232         .port_a_write_input(a_write_input[23:16]),
 233         .port_a_read_output(a_read_output_3[23:16]),
 234         .port_b_address(b_ram_address[10:0]),
 235         .port_b_read_output(b_read_output_3[23:16])
 236         );
 237
 238     block_memory_16kbit #(
 239         .initial_file("software/ram_3_byte3.hex")
 240         ) ram_3_byte3(
 241         .clk(clk),
 242         .port_a_address(a_ram_address[10:0]),
 243         .port_a_write_enable(a_write_enable_3[3]),
 244         .port_a_write_input(a_write_input[31:24]),
 245         .port_a_read_output(a_read_output_3[31:24]),
 246         .port_b_address(b_ram_address[10:0]),
 247         .port_b_read_output(b_read_output_3[31:24])
 248         );
 249
 250
 251     always @* begin
 252         case(a_ram_address[31:11])
 253         0: a_read_output = a_read_output_0;
 254         1: a_read_output = a_read_output_1;
 255         2: a_read_output = a_read_output_2;
 256         3: a_read_output = a_read_output_3;
 257         default: a_read_output = 32'hXXXXXXXX;
 258         endcase
 259     end
 260
 261     always @* begin
 262         case(b_ram_address[31:11])
 263         0: b_read_output = b_read_output_0;
 264         1: b_read_output = b_read_output_1;
 265         2: b_read_output = b_read_output_2;
 266         3: b_read_output = b_read_output_3;
 267         default: b_read_output = 32'hXXXXXXXX;
 268         endcase
 269     end
 270 endmodule