cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 import string
  30 from migen import *
  31 from migen.fhdl import verilog
  32 from migen.fhdl.structure import _Operator
  33
  34 from riscvdefs import *
  35 from cpudefs import *
  36
  37 class MemoryInterface:
  38     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  39     fetch_data = Signal(32, name="memory_interface_fetch_data")
  40     fetch_valid = Signal(name="memory_interface_fetch_valid")
  41     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  42     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  43     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  44     rw_active = Signal(name="memory_interface_rw_active")
  45     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  46     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  47     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  48     rw_wait = Signal(name="memory_interface_rw_wait")
  49
  50
  51 class Decoder:
  52     funct7 = Signal(7, name="decoder_funct7")
  53     funct3 = Signal(3, name="decoder_funct3")
  54     rd = Signal(5, name="decoder_rd")
  55     rs1 = Signal(5, name="decoder_rs1")
  56     rs2 = Signal(5, name="decoder_rs2")
  57     immediate = Signal(32, name="decoder_immediate")
  58     opcode = Signal(7, name="decoder_opcode")
  59     act = Signal(decode_action, name="decoder_action")
  60
  61
  62 class MStatus:
  63     def __init__(self, comb, sync):
  64         self.comb = comb
  65         self.sync = sync
  66         self.mpie = Signal(name="mstatus_mpie")
  67         self.mie = Signal(name="mstatus_mie")
  68         self.mstatus = Signal(32, name="mstatus")
  69
  70         self.sync += self.mie.eq(0)
  71         self.sync += self.mpie.eq(0)
  72         self.sync += self.mstatus.eq(0)
  73
  74
  75 class MIE:
  76     def __init__(self, comb, sync):
  77         self.comb = comb
  78         self.sync = sync
  79         self.meie = Signal(name="mie_meie")
  80         self.mtie = Signal(name="mie_mtie")
  81         self.msie = Signal(name="mie_msie")
  82         self.mie = Signal(32)
  83
  84
  85 class MIP:
  86     def __init__(self, comb, sync):
  87         self.comb = comb
  88         self.sync = sync
  89         self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts
  90         self.seip = Signal(name="mip_seip")
  91         self.ueip = Signal(name="mip_uiep")
  92         self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts
  93         self.stip = Signal(name="mip_stip")
  94         self.msip = Signal(name="mip_stip")
  95         self.utip = Signal(name="mip_utip")
  96         self.ssip = Signal(name="mip_ssip")
  97         self.usip = Signal(name="mip_usip")
  98
  99         for n in dir(self):
 100             if n in ['make', 'comb', 'sync'] or n.startswith("_"):
 101                 continue
 102             self.comb += getattr(self, n).eq(0x0)
 103
 104     def make(self):
 105         return Cat( self.usip, self.ssip, 0, self.msip,
 106                     self.utip, self.stip, 0, self.mtip,
 107                     self.ueip, self.seip, 0, self.meip, )
 108
 109
 110 class M:
 111     def __init__(self, comb, sync):
 112         self.comb = comb
 113         self.sync = sync
 114         self.mcause = Signal(32)
 115         self.mepc = Signal(32)
 116         self.mscratch = Signal(32)
 117         self.sync += self.mcause.eq(0)
 118         self.sync += self.mepc.eq(0) # 32'hXXXXXXXX;
 119         self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
 120
 121
 122 class Misa:
 123     def __init__(self, comb, sync):
 124         self.comb = comb
 125         self.sync = sync
 126         self.misa = Signal(32)
 127         cl = []
 128         for l in list(string.ascii_lowercase):
 129             value = 1 if l == 'i' else 0
 130             cl.append(Constant(value))
 131         cl.append(Constant(0, 4))
 132         cl.append(Constant(0b01, 2))
 133         self.comb += self.misa.eq(Cat(cl))
 134
 135
 136 class Fetch:
 137     def __init__(self, comb, sync):
 138         self.comb = comb
 139         self.sync = sync
 140         self.action = Signal(fetch_action, name="fetch_action")
 141         self.target_pc = Signal(32, name="fetch_target_pc")
 142         self.output_pc = Signal(32, name="fetch_output_pc")
 143         self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
 144         self.output_state = Signal(fetch_output_state,name="fetch_output_state")
 145
 146 class CSR:
 147     def __init__(self, comb, sync, dc, register_rs1):
 148         self.comb = comb
 149         self.sync = sync
 150         self.number = Signal(12, name="csr_number")
 151         self.input_value = Signal(32, name="csr_input_value")
 152         self.reads = Signal(name="csr_reads")
 153         self.writes = Signal(name="csr_writes")
 154         self.op_is_valid = Signal(name="csr_op_is_valid")
 155
 156         self.comb += self.number.eq(dc.immediate)
 157         self.comb += self.input_value.eq(Mux(dc.funct3[2],
 158                                             dc.rs1,
 159                                             register_rs1))
 160         self.comb += self.reads.eq(dc.funct3[1] | (dc.rd != 0))
 161         self.comb += self.writes.eq(~dc.funct3[1] | (dc.rs1 != 0))
 162
 163         self.comb += self.get_csr_op_is_valid()
 164
 165     def get_csr_op_is_valid(self):
 166         """ determines if a CSR is valid
 167         """
 168         c = {}
 169         # invalid csrs
 170         for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr,
 171                   csr_uie, csr_utvec, csr_uscratch, csr_uepc,
 172                   csr_ucause, csr_utval, csr_uip, csr_sstatus,
 173                   csr_sedeleg, csr_sideleg, csr_sie, csr_stvec,
 174                   csr_scounteren, csr_sscratch, csr_sepc, csr_scause,
 175                   csr_stval, csr_sip, csr_satp, csr_medeleg,
 176                   csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]:
 177             c[f] = self.op_is_valid.eq(0)
 178
 179         # not-writeable -> ok
 180         for f in [csr_cycle, csr_time, csr_instret, csr_cycleh,
 181                   csr_timeh, csr_instreth, csr_mvendorid, csr_marchid,
 182                   csr_mimpid, csr_mhartid]:
 183             c[f] = self.op_is_valid.eq(~self.writes)
 184
 185         # valid csrs
 186         for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec,
 187                   csr_mscratch, csr_mepc, csr_mcause, csr_mip]:
 188             c[f] = self.op_is_valid.eq(1)
 189
 190         # not implemented / default
 191         for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret,
 192                   csr_mcycleh, csr_minstreth, "default"]:
 193             c[f] = self.op_is_valid.eq(0)
 194
 195         return Case(self.number, c)
 196
 197     def evaluate_csr_funct3_op(self, funct3, previous, written):
 198         c = { "default": written.eq(Constant(0, 32))}
 199         for f in [F3.csrrw, F3.csrrwi]:
 200             c[f] = written.eq(self.input_value)
 201         for f in [F3.csrrs, F3.csrrsi]:
 202             c[f] = written.eq(self.input_value | previous)
 203         for f in [F3.csrrc, F3.csrrci]:
 204             c[f] = written.eq(~self.input_value & previous)
 205         return Case(funct3, c)
 206
 207
 208 class MInfo:
 209     def __init__(self, comb):
 210         self.comb = comb
 211         # TODO
 212         self.cycle_counter   = Signal(64); # TODO: implement cycle_counter
 213         self.time_counter    = Signal(64); # TODO: implement time_counter
 214         self.instret_counter = Signal(64); # TODO: implement instret_counter
 215
 216         self.mvendorid = Signal(32)
 217         self.marchid = Signal(32)
 218         self.mimpid = Signal(32)
 219         self.mhartid = Signal(32)
 220         self.comb += self.mvendorid.eq(Constant(0, 32))
 221         self.comb += self.marchid.eq(Constant(0, 32))
 222         self.comb += self.mimpid.eq(Constant(0, 32))
 223         self.comb += self.mhartid.eq(Constant(0, 32))
 224
 225 class Regs:
 226     def __init__(self, comb, sync):
 227         self.comb = comb
 228         self.sync = sync
 229
 230         self.ra_en = Signal(reset=1, name="regfile_ra_en") # TODO: ondemand en
 231         self.rs1 = Signal(32, name="regfile_rs1")
 232         self.rs_a = Signal(5, name="regfile_rs_a")
 233
 234         self.rb_en = Signal(reset=1, name="regfile_rb_en") # TODO: ondemand en
 235         self.rs2 = Signal(32, name="regfile_rs2")
 236         self.rs_b = Signal(5, name="regfile_rs_b")
 237
 238         self.w_en = Signal(name="regfile_w_en")
 239         self.wval = Signal(32, name="regfile_wval")
 240         self.rd = Signal(32, name="regfile_rd")
 241
 242 class CPU(Module):
 243     """
 244     """
 245
 246     def get_lsbm(self, dc):
 247         return Cat(Constant(1),
 248                    Mux((dc.funct3[1] | dc.funct3[0]),
 249                        Constant(1), Constant(0)),
 250                    Mux((dc.funct3[1]),
 251                        Constant(0b11, 2), Constant(0, 2)))
 252
 253     # XXX this happens to get done by various self.sync actions
 254     #def reset_to_initial(self, m, mstatus, mie, registers):
 255     #    return [m.mcause.eq(0),
 256     #            ]
 257
 258     def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
 259         s = [ms.mpie.eq(ms.mie),
 260              ms.mie.eq(0),
 261              m.mepc.eq(Mux(ft.action == FA.noerror_trap,
 262                            ft.output_pc + 4,
 263                            ft.output_pc))]
 264
 265         # fetch action ack trap
 266         i = If(ft.action == FA.ack_trap,
 267                 m.mcause.eq(cause_instruction_access_fault)
 268               )
 269
 270         # ecall/ebreak
 271         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
 272                 m.mcause.eq(Mux(dc.immediate[0],
 273                                 cause_machine_environment_call,
 274                                 cause_breakpoint))
 275               )
 276
 277         # load
 278         i = i.Elif((dc.act & DA.load) != 0,
 279                 If(load_store_misaligned,
 280                     m.mcause.eq(cause_load_address_misaligned)
 281                 ).Else(
 282                     m.mcause.eq(cause_load_access_fault)
 283                 )
 284               )
 285
 286         # store
 287         i = i.Elif((dc.act & DA.store) != 0,
 288                 If(load_store_misaligned,
 289                     m.mcause.eq(cause_store_amo_address_misaligned)
 290                 ).Else(
 291                     m.mcause.eq(cause_store_amo_access_fault)
 292                 )
 293               )
 294
 295         # jal/jalr -> misaligned=error, otherwise jump
 296         i = i.Elif((dc.act & (DA.jal | DA.jalr | DA.branch)) != 0,
 297                 m.mcause.eq(cause_instruction_address_misaligned)
 298               )
 299
 300         # defaults to illegal instruction
 301         i = i.Else(m.mcause.eq(cause_illegal_instruction))
 302
 303         s.append(i)
 304         return s
 305
 306     def main_block(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
 307                          ft, dc,
 308                          load_store_misaligned,
 309                          loaded_value, alu_result,
 310                          lui_auipc_result):
 311         c = {}
 312         c[FOS.empty] = []
 313         c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc,
 314                                        load_store_misaligned)
 315         c[FOS.valid] = self.handle_valid(mtvec, mip, minfo, misa, csr, mi, m,
 316                                        mstatus, mie, ft, dc,
 317                                        load_store_misaligned,
 318                                        loaded_value,
 319                                        alu_result,
 320                                        lui_auipc_result)
 321         return Case(ft.output_state, c)
 322
 323     def write_register(self, rd, val):
 324         return [self.regs.rd.eq(rd),
 325                 self.regs.wval.eq(val),
 326                 self.regs.w_en.eq(1)
 327                ]
 328
 329     def handle_valid(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
 330                            ft, dc,
 331                            load_store_misaligned,
 332                            loaded_value, alu_result,
 333                            lui_auipc_result):
 334         # fetch action ack trap
 335         i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
 336                 [self.handle_trap(m, mstatus, ft, dc,
 337                                        load_store_misaligned),
 338                  self.regs.w_en.eq(0) # no writing to registers
 339                 ]
 340               )
 341
 342         # load
 343         i = i.Elif((dc.act & DA.load) != 0,
 344                 If(~mi.rw_wait,
 345                     self.write_register(dc.rd, loaded_value)
 346                 )
 347               )
 348
 349         # op or op_immediate
 350         i = i.Elif((dc.act & DA.op_op_imm) != 0,
 351                 self.write_register(dc.rd, alu_result)
 352               )
 353
 354         # lui or auipc
 355         i = i.Elif((dc.act & DA.lui_auipc) != 0,
 356                 self.write_register(dc.rd, lui_auipc_result)
 357               )
 358
 359         # jal/jalr
 360         i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
 361                 self.write_register(dc.rd, ft.output_pc + 4)
 362               )
 363
 364         i = i.Elif((dc.act & DA.csr) != 0,
 365                 self.handle_csr(mtvec, mip, minfo, misa, mstatus, mie, m,
 366                                 dc, csr)
 367               )
 368
 369         # fence, store, branch
 370         i = i.Elif((dc.act & (DA.fence | DA.fence_i |
 371                               DA.store | DA.branch)) != 0,
 372                 # do nothing
 373                self.regs.w_en.eq(0) # no writing to registers
 374               )
 375
 376         return i
 377
 378     def handle_csr(self, mtvec, mip, minfo, misa, mstatus, mie, m, dc, csr):
 379         csr_output_value = Signal(32)
 380         csr_written_value = Signal(32)
 381         c = {}
 382
 383         # cycle
 384         c[csr_cycle]  = csr_output_value.eq(minfo.cycle_counter[0:32])
 385         c[csr_cycleh] = csr_output_value.eq(minfo.cycle_counter[32:64])
 386         # time
 387         c[csr_time]  = csr_output_value.eq(minfo.time_counter[0:32])
 388         c[csr_timeh] = csr_output_value.eq(minfo.time_counter[32:64])
 389         # instret
 390         c[csr_instret]  = csr_output_value.eq(minfo.instret_counter[0:32])
 391         c[csr_instreth] = csr_output_value.eq(minfo.instret_counter[32:64])
 392         # mvendorid/march/mimpl/mhart
 393         c[csr_mvendorid] = csr_output_value.eq(minfo.mvendorid)
 394         c[csr_marchid  ] = csr_output_value.eq(minfo.marchid  )
 395         c[csr_mimpid   ] = csr_output_value.eq(minfo.mimpid   )
 396         c[csr_mhartid  ] = csr_output_value.eq(minfo.mhartid  )
 397         # misa
 398         c[csr_misa     ] = csr_output_value.eq(misa.misa)
 399         # mstatus
 400         c[csr_mstatus  ] = [
 401             csr_output_value.eq(mstatus.mstatus),
 402             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 403                                                   csr_written_value),
 404             mstatus.mpie.eq(csr_written_value[7]),
 405             mstatus.mie.eq(csr_written_value[3])
 406         ]
 407         # mie
 408         c[csr_mie      ] = [
 409             csr_output_value.eq(mie.mie),
 410             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 411                                                   csr_written_value),
 412             mie.meie.eq(csr_written_value[11]),
 413             mie.mtie.eq(csr_written_value[7]),
 414             mie.msie.eq(csr_written_value[3]),
 415         ]
 416         # mtvec
 417         c[csr_mtvec    ] = csr_output_value.eq(mtvec)
 418         # mscratch
 419         c[csr_mscratch ] = [
 420             csr_output_value.eq(m.mscratch),
 421             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 422                                                   csr_written_value),
 423             If(csr.writes,
 424                 m.mscratch.eq(csr_written_value),
 425             )
 426         ]
 427         # mepc
 428         c[csr_mepc ] = [
 429             csr_output_value.eq(m.mepc),
 430             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 431                                                   csr_written_value),
 432             If(csr.writes,
 433                 m.mepc.eq(csr_written_value),
 434             )
 435         ]
 436
 437         # mcause
 438         c[csr_mcause ] = [
 439             csr_output_value.eq(m.mcause),
 440             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 441                                                   csr_written_value),
 442             If(csr.writes,
 443                 m.mcause.eq(csr_written_value),
 444             )
 445         ]
 446
 447         # mip
 448         c[csr_mip  ] = [
 449             csr_output_value.eq(mip.make()),
 450             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 451                                                   csr_written_value),
 452         ]
 453
 454         return [Case(csr.number, c),
 455                 If(csr.reads,
 456                     self.write_register(dc.rd, csr_output_value)
 457                 )]
 458
 459     def __init__(self):
 460         Module.__init__(self)
 461         self.clk = ClockSignal()
 462         self.reset = ResetSignal()
 463         self.tty_write = Signal()
 464         self.tty_write_data = Signal(8)
 465         self.tty_write_busy = Signal()
 466         self.switch_2 = Signal()
 467         self.switch_3 = Signal()
 468         self.led_1 = Signal()
 469         self.led_3 = Signal()
 470
 471         ram_size = Constant(0x8000)
 472         ram_start = Constant(0x10000, 32)
 473         reset_vector = Signal(32)
 474         mtvec = Signal(32)
 475
 476         reset_vector.eq(ram_start)
 477         mtvec.eq(ram_start + 0x40)
 478
 479         self.regs = Regs(self.comb, self.sync)
 480
 481         rf = Instance("RegFile", name="regfile",
 482            i_ra_en = self.regs.ra_en,
 483            i_rb_en = self.regs.rb_en,
 484            i_w_en = self.regs.w_en,
 485            o_read_a = self.regs.rs1,
 486            o_read_b = self.regs.rs2,
 487            i_writeval = self.regs.wval,
 488            i_rs_a = self.regs.rs_a,
 489            i_rs_b = self.regs.rs_b,
 490            i_rd = self.regs.rd)
 491
 492         self.specials += rf
 493
 494         mi = MemoryInterface()
 495
 496         mii = Instance("cpu_memory_interface", name="memory_instance",
 497                     p_ram_size = ram_size,
 498                     p_ram_start = ram_start,
 499                     i_clk=ClockSignal(),
 500                     i_rst=ResetSignal(),
 501                     i_fetch_address = mi.fetch_address,
 502                     o_fetch_data = mi.fetch_data,
 503                     o_fetch_valid = mi.fetch_valid,
 504                     i_rw_address = mi.rw_address,
 505                     i_rw_byte_mask = mi.rw_byte_mask,
 506                     i_rw_read_not_write = mi.rw_read_not_write,
 507                     i_rw_active = mi.rw_active,
 508                     i_rw_data_in = mi.rw_data_in,
 509                     o_rw_data_out = mi.rw_data_out,
 510                     o_rw_address_valid = mi.rw_address_valid,
 511                     o_rw_wait = mi.rw_wait,
 512                     o_tty_write = self.tty_write,
 513                     o_tty_write_data = self.tty_write_data,
 514                     i_tty_write_busy = self.tty_write_busy,
 515                     i_switch_2 = self.switch_2,
 516                     i_switch_3 = self.switch_3,
 517                     o_led_1 = self.led_1,
 518                     o_led_3 = self.led_3
 519                   )
 520         self.specials += mii
 521
 522         ft = Fetch(self.comb, self.sync)
 523
 524         fs = Instance("CPUFetchStage", name="fetch_stage",
 525             i_clk=ClockSignal(),
 526             i_rst=ResetSignal(),
 527             o_memory_interface_fetch_address = mi.fetch_address,
 528             i_memory_interface_fetch_data = mi.fetch_data,
 529             i_memory_interface_fetch_valid = mi.fetch_valid,
 530             i_fetch_action = ft.action,
 531             i_target_pc = ft.target_pc,
 532             o_output_pc = ft.output_pc,
 533             o_output_instruction = ft.output_instruction,
 534             o_output_state = ft.output_state,
 535             i_reset_vector = reset_vector,
 536             i_mtvec = mtvec,
 537         )
 538         self.specials += fs
 539
 540         dc = Decoder()
 541
 542         cd = Instance("CPUDecoder", name="decoder",
 543             i_instruction = ft.output_instruction,
 544             o_funct7 = dc.funct7,
 545             o_funct3 = dc.funct3,
 546             o_rd = dc.rd,
 547             o_rs1 = dc.rs1,
 548             o_rs2 = dc.rs2,
 549             o_immediate = dc.immediate,
 550             o_opcode = dc.opcode,
 551             o_decode_action = dc.act
 552         )
 553         self.specials += cd
 554
 555         self.comb += self.regs.rs_a.eq(dc.rs1)
 556         self.comb += self.regs.rs_b.eq(dc.rs2)
 557
 558         load_store_address = Signal(32)
 559         load_store_address_low_2 = Signal(2)
 560         load_store_misaligned = Signal()
 561         unmasked_loaded_value = Signal(32)
 562         loaded_value = Signal(32)
 563
 564         lsc = Instance("CPULoadStoreCalc", name="cpu_loadstore_calc",
 565             i_dc_immediate = dc.immediate,
 566             i_dc_funct3 = dc.funct3,
 567             i_rs1 = self.regs.rs1,
 568             i_rs2 = self.regs.rs2,
 569             i_rw_data_in = mi.rw_data_in,
 570             i_rw_data_out = mi.rw_data_out,
 571             o_load_store_address = load_store_address,
 572             o_load_store_address_low_2 = load_store_address_low_2,
 573             o_load_store_misaligned = load_store_misaligned,
 574             o_loaded_value = loaded_value)
 575
 576         self.specials += lsc
 577
 578         # XXX rwaddr not 31:2 any more
 579         self.comb += mi.rw_address.eq(load_store_address[2:])
 580
 581         unshifted_load_store_byte_mask = Signal(4)
 582
 583         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc))
 584
 585         # XXX yuck.  this will cause migen simulation to fail
 586         # (however conversion to verilog works)
 587         self.comb += mi.rw_byte_mask.eq(
 588                 _Operator("<<", [unshifted_load_store_byte_mask,
 589                                         load_store_address_low_2]))
 590
 591         self.comb += mi.rw_active.eq(~self.reset
 592                         & (ft.output_state == FOS.valid)
 593                         & ~load_store_misaligned
 594                         & ((dc.act & (DA.load | DA.store)) != 0))
 595
 596         self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
 597
 598         # alu
 599         alu_a = Signal(32)
 600         alu_b = Signal(32)
 601         alu_result = Signal(32)
 602
 603         self.comb += alu_a.eq(self.regs.rs1)
 604         self.comb += alu_b.eq(Mux(dc.opcode[5],
 605                                   self.regs.rs2,
 606                                   dc.immediate))
 607
 608         ali = Instance("cpu_alu", name="alu",
 609             i_funct7 = dc.funct7,
 610             i_funct3 = dc.funct3,
 611             i_opcode = dc.opcode,
 612             i_a = alu_a,
 613             i_b = alu_b,
 614             o_result = alu_result
 615         )
 616         self.specials += ali
 617
 618         lui_auipc_result = Signal(32)
 619         self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
 620                                              dc.immediate,
 621                                              dc.immediate + ft.output_pc))
 622
 623         self.comb += ft.target_pc.eq(Cat(0,
 624                     Mux(dc.opcode != OP.jalr,
 625                                 ft.output_pc[1:32],
 626                                 self.regs.rs1[1:32] + dc.immediate[1:32])))
 627
 628         misaligned_jump_target = Signal()
 629         self.comb += misaligned_jump_target.eq(ft.target_pc[1])
 630
 631         branch_arg_a = Signal(32)
 632         branch_arg_b = Signal(32)
 633         self.comb += branch_arg_a.eq(Cat( self.regs.rs1[0:31],
 634                                           self.regs.rs1[31] ^ ~dc.funct3[1]))
 635         self.comb += branch_arg_b.eq(Cat( self.regs.rs2[0:31],
 636                                           self.regs.rs2[31] ^ ~dc.funct3[1]))
 637
 638         branch_taken = Signal()
 639         self.comb += branch_taken.eq(dc.funct3[0] ^
 640                                      Mux(dc.funct3[2],
 641                                          branch_arg_a < branch_arg_b,
 642                                          branch_arg_a == branch_arg_b))
 643
 644         m = M(self.comb, self.sync)
 645         mstatus = MStatus(self.comb, self.sync)
 646         mie = MIE(self.comb, self.sync)
 647         misa = Misa(self.comb, self.sync)
 648         mip = MIP(self.comb, self.sync)
 649
 650         mii = Instance("CPUMIE", name="cpu_mie",
 651             o_mie = mie.mie,
 652             i_meie = mie.meie,
 653             i_mtie = mie.mtie,
 654             i_msie = mie.msie)
 655
 656         self.specials += mii
 657
 658         ms = Instance("CPUMStatus", name="cpu_mstatus",
 659             o_mstatus = mstatus.mstatus,
 660             i_mpie = mstatus.mpie,
 661             i_mie = mstatus.mie)
 662
 663         self.specials += ms
 664
 665         # CSR decoding
 666         csr = CSR(self.comb, self.sync, dc, self.regs.rs1)
 667
 668         fi = Instance("CPUFetchAction", name="cpu_fetch_action",
 669             o_fetch_action = ft.action,
 670             i_output_state = ft.output_state,
 671             i_dc_act = dc.act,
 672             i_load_store_misaligned = load_store_misaligned,
 673             i_mi_rw_wait = mi.rw_wait,
 674             i_mi_rw_address_valid = mi.rw_address_valid,
 675             i_branch_taken = branch_taken,
 676             i_misaligned_jump_target = misaligned_jump_target,
 677             i_csr_op_is_valid = csr.op_is_valid)
 678
 679         self.specials += fi
 680
 681         minfo = MInfo(self.comb)
 682
 683         self.sync += If(~self.reset,
 684                         self.main_block(mtvec, mip, minfo, misa, csr, mi, m,
 685                                         mstatus, mie, ft, dc,
 686                                         load_store_misaligned,
 687                                         loaded_value,
 688                                        alu_result,
 689                                        lui_auipc_result)
 690                      )
 691
 692 if __name__ == "__main__":
 693     example = CPU()
 694     print(verilog.convert(example,
 695          {
 696            example.tty_write,
 697            example.tty_write_data,
 698            example.tty_write_busy,
 699            example.switch_2,
 700            example.switch_3,
 701            example.led_1,
 702            example.led_3,
 703            }))