cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 from migen import *
  30 from migen.fhdl import verilog
  31
  32 from riscvdefs import *
  33 from cpudefs import *
  34
  35 class MemoryInterface:
  36     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  37     fetch_data = Signal(32, name="memory_interface_fetch_data")
  38     fetch_valid = Signal(name="memory_interface_fetch_valid")
  39     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  40     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  41     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  42     rw_active = Signal(name="memory_interface_rw_active")
  43     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  44     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  45     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  46     rw_wait = Signal(name="memory_interface_rw_wait")
  47
  48
  49 class CPU(Module):
  50     """
  51     """
  52
  53     def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
  54         return Case(funct3[:2],
  55                 { F3.sb: ls.eq(Constant(0)),
  56                   F3.sh: ls.eq(load_store_address_low_2[0] != 0),
  57                   F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
  58                   "default": ls.eq(Constant(1))
  59                 })
  60
  61     def __init__(self):
  62         #self.clk = ClockSignal()
  63         #self.reset = ResetSignal()
  64         self.tty_write = Signal()
  65         self.tty_write_data = Signal(8)
  66         self.tty_write_busy = Signal()
  67         self.switch_2 = Signal()
  68         self.switch_3 = Signal()
  69         self.led_1 = Signal()
  70         self.led_3 = Signal()
  71
  72         ram_size = Constant(0x8000)
  73         ram_start = Constant(0x10000, 32)
  74         reset_vector = Signal(32)
  75         mtvec = Signal(32)
  76
  77         reset_vector.eq(ram_start)
  78         mtvec.eq(ram_start + 0x40)
  79
  80         l = []
  81         for i in range(31):
  82             l.append(Signal(32, name="register%d" % i))
  83         registers = Array(l)
  84
  85         #self.sync += self.registers[0].eq(0)
  86         #self.sync += self.registers[1].eq(0)
  87
  88         mi = MemoryInterface()
  89
  90         mii = Instance("cpu_memory_interface", name="memory_instance",
  91                     p_ram_size = ram_size,
  92                     p_ram_start = ram_start,
  93                     i_clk=ClockSignal(),
  94                     i_rst=ResetSignal(),
  95                     i_fetch_address = mi.fetch_address,
  96                     o_fetch_data = mi.fetch_data,
  97                     o_fetch_valid = mi.fetch_valid,
  98                     i_rw_address = mi.rw_address,
  99                     i_rw_byte_mask = mi.rw_byte_mask,
 100                     i_rw_read_not_write = mi.rw_read_not_write,
 101                     i_rw_active = mi.rw_active,
 102                     i_rw_data_in = mi.rw_data_in,
 103                     o_rw_data_out = mi.rw_data_out,
 104                     o_rw_address_valid = mi.rw_address_valid,
 105                     o_rw_wait = mi.rw_wait,
 106                     o_tty_write = self.tty_write,
 107                     o_tty_write_data = self.tty_write_data,
 108                     i_tty_write_busy = self.tty_write_busy,
 109                     i_switch_2 = self.switch_2,
 110                     i_switch_3 = self.switch_3,
 111                     o_led_1 = self.led_1,
 112                     o_led_3 = self.led_3
 113                   )
 114         self.specials += mii
 115
 116         fetch_act = Signal(fetch_action)
 117         fetch_target_pc = Signal(32)
 118         fetch_output_pc = Signal(32)
 119         fetch_output_instruction = Signal(32)
 120         fetch_output_st = Signal(fetch_output_state)
 121
 122         fs = Instance("CPUFetchStage", name="fetch_stage",
 123             i_clk=ClockSignal(),
 124             i_rst=ResetSignal(),
 125             o_memory_interface_fetch_address = mi.fetch_address,
 126             i_memory_interface_fetch_data = mi.fetch_data,
 127             i_memory_interface_fetch_valid = mi.fetch_valid,
 128             i_fetch_action = fetch_act,
 129             i_target_pc = fetch_target_pc,
 130             o_output_pc = fetch_output_pc,
 131             o_output_instruction = fetch_output_instruction,
 132             o_output_state = fetch_output_st,
 133             i_reset_vector = reset_vector,
 134             i_mtvec = mtvec,
 135         )
 136         self.specials += fs
 137
 138         decoder_funct7 = Signal(7)
 139         decoder_funct3 = Signal(3)
 140         decoder_rd = Signal(5)
 141         decoder_rs1 = Signal(5)
 142         decoder_rs2 = Signal(5)
 143         decoder_immediate = Signal(32)
 144         decoder_opcode = Signal(7)
 145         decode_act = Signal(decode_action)
 146
 147         cd = Instance("CPUDecoder", name="decoder",
 148             i_instruction = fetch_output_instruction,
 149             o_funct7 = decoder_funct7,
 150             o_funct3 = decoder_funct3,
 151             o_rd = decoder_rd,
 152             o_rs1 = decoder_rs1,
 153             o_rs2 = decoder_rs2,
 154             o_immediate = decoder_immediate,
 155             o_opcode = decoder_opcode,
 156             o_decode_action = decode_act
 157         )
 158         self.specials += cd
 159
 160         register_rs1 = Signal(32)
 161         register_rs2 = Signal(32)
 162         self.comb += If(decoder_rs1 == 0,
 163                         register_rs1.eq(0)
 164                      ).Else(
 165                         register_rs1.eq(registers[decoder_rs1-1]))
 166         self.comb += If(decoder_rs2 == 0,
 167                         register_rs2.eq(0)
 168                      ).Else(
 169                         register_rs2.eq(registers[decoder_rs2-1]))
 170
 171         load_store_address = Signal(32)
 172         load_store_address_low_2 = Signal(2)
 173
 174         self.comb += load_store_address.eq(decoder_immediate + register_rs1)
 175         self.comb += load_store_address_low_2.eq(
 176                             decoder_immediate[:2] + register_rs1[:2])
 177
 178         load_store_misaligned = Signal()
 179
 180         lsa = self.get_ls_misaligned(load_store_misaligned, decoder_funct3,
 181                                      load_store_address_low_2)
 182         self.comb += lsa
 183
 184
 185 if __name__ == "__main__":
 186     example = CPU()
 187     print(verilog.convert(example,
 188          {
 189            example.tty_write,
 190            example.tty_write_data,
 191            example.tty_write_busy,
 192            example.switch_2,
 193            example.switch_3,
 194            example.led_1,
 195            example.led_3,
 196            }))
 197
 198 """
 199
 200     assign memory_interface_rw_address = load_store_address[31:2];
 201
 202     wire [3:0] unshifted_load_store_byte_mask = {decoder_funct3[1] ? 2'b11 : 2'b00, (decoder_funct3[1] | decoder_funct3[0]) ? 1'b1 : 1'b0, 1'b1};
 203
 204     assign memory_interface_rw_byte_mask = unshifted_load_store_byte_mask << load_store_address_low_2;
 205
 206     assign memory_interface_rw_data_in[31:24] = load_store_address_low_2[1]
 207                                                 ? (load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8])
 208                                                 : (load_store_address_low_2[0] ? register_rs2[23:16] : register_rs2[31:24]);
 209     assign memory_interface_rw_data_in[23:16] = load_store_address_low_2[1] ? register_rs2[7:0] : register_rs2[23:16];
 210     assign memory_interface_rw_data_in[15:8] = load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8];
 211     assign memory_interface_rw_data_in[7:0] = register_rs2[7:0];
 212
 213     wire [31:0] unmasked_loaded_value;
 214
 215     assign unmasked_loaded_value[7:0] = load_store_address_low_2[1]
 216                                         ? (load_store_address_low_2[0] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[23:16])
 217                                         : (load_store_address_low_2[0] ? memory_interface_rw_data_out[15:8] : memory_interface_rw_data_out[7:0]);
 218     assign unmasked_loaded_value[15:8] = load_store_address_low_2[1] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[15:8];
 219     assign unmasked_loaded_value[31:16] = memory_interface_rw_data_out[31:16];
 220
 221     wire [31:0] loaded_value;
 222
 223     assign loaded_value[7:0] = unmasked_loaded_value[7:0];
 224     assign loaded_value[15:8] = decoder_funct3[1:0] == 0 ? ({8{~decoder_funct3[2] & unmasked_loaded_value[7]}}) : unmasked_loaded_value[15:8];
 225     assign loaded_value[31:16] = decoder_funct3[1] == 0 ? ({16{~decoder_funct3[2] & (decoder_funct3[0] ? unmasked_loaded_value[15] : unmasked_loaded_value[7])}}) : unmasked_loaded_value[31:16];
 226
 227     assign memory_interface_rw_active = ~reset
 228                                         & (fetch_output_state == `fetch_output_state_valid)
 229                                         & ~load_store_misaligned
 230                                         & ((decode_action & (`decode_action_load | `decode_action_store)) != 0);
 231
 232     assign memory_interface_rw_read_not_write = ~decoder_opcode[5];
 233
 234     wire [31:0] alu_a = register_rs1;
 235     wire [31:0] alu_b = decoder_opcode[5] ? register_rs2 : decoder_immediate;
 236     wire [31:0] alu_result;
 237
 238     cpu_alu alu(
 239         .funct7(decoder_funct7),
 240         .funct3(decoder_funct3),
 241         .opcode(decoder_opcode),
 242         .a(alu_a),
 243         .b(alu_b),
 244         .result(alu_result)
 245         );
 246
 247     wire [31:0] lui_auipc_result = decoder_opcode[5] ? decoder_immediate : decoder_immediate + fetch_output_pc;
 248
 249     assign fetch_target_pc[31:1] = ((decoder_opcode != `opcode_jalr ? fetch_output_pc[31:1] : register_rs1[31:1]) + decoder_immediate[31:1]);
 250     assign fetch_target_pc[0] = 0;
 251
 252     wire misaligned_jump_target = fetch_target_pc[1];
 253
 254     wire [31:0] branch_arg_a = {register_rs1[31] ^ ~decoder_funct3[1], register_rs1[30:0]};
 255     wire [31:0] branch_arg_b = {register_rs2[31] ^ ~decoder_funct3[1], register_rs2[30:0]};
 256
 257     wire branch_taken = decoder_funct3[0] ^ (decoder_funct3[2] ? branch_arg_a < branch_arg_b : branch_arg_a == branch_arg_b);
 258
 259     reg [31:0] mcause = 0;
 260     reg [31:0] mepc = 32'hXXXXXXXX;
 261     reg [31:0] mscratch = 32'hXXXXXXXX;
 262
 263     reg mstatus_mpie = 1'bX;
 264     reg mstatus_mie = 0;
 265     parameter mstatus_mprv = 0;
 266     parameter mstatus_tsr = 0;
 267     parameter mstatus_tw = 0;
 268     parameter mstatus_tvm = 0;
 269     parameter mstatus_mxr = 0;
 270     parameter mstatus_sum = 0;
 271     parameter mstatus_xs = 0;
 272     parameter mstatus_fs = 0;
 273     parameter mstatus_mpp = 2'b11;
 274     parameter mstatus_spp = 0;
 275     parameter mstatus_spie = 0;
 276     parameter mstatus_upie = 0;
 277     parameter mstatus_sie = 0;
 278     parameter mstatus_uie = 0;
 279
 280     reg mie_meie = 1'bX;
 281     reg mie_mtie = 1'bX;
 282     reg mie_msie = 1'bX;
 283     parameter mie_seie = 0;
 284     parameter mie_ueie = 0;
 285     parameter mie_stie = 0;
 286     parameter mie_utie = 0;
 287     parameter mie_ssie = 0;
 288     parameter mie_usie = 0;
 289
 290     task reset_to_initial;
 291     begin
 292         mcause = 0;
 293         mepc = 32'hXXXXXXXX;
 294         mscratch = 32'hXXXXXXXX;
 295         mstatus_mie = 0;
 296         mstatus_mpie = 1'bX;
 297         mie_meie = 1'bX;
 298         mie_mtie = 1'bX;
 299         mie_msie = 1'bX;
 300         registers['h01] <= 32'hXXXXXXXX;
 301         registers['h02] <= 32'hXXXXXXXX;
 302         registers['h03] <= 32'hXXXXXXXX;
 303         registers['h04] <= 32'hXXXXXXXX;
 304         registers['h05] <= 32'hXXXXXXXX;
 305         registers['h06] <= 32'hXXXXXXXX;
 306         registers['h07] <= 32'hXXXXXXXX;
 307         registers['h08] <= 32'hXXXXXXXX;
 308         registers['h09] <= 32'hXXXXXXXX;
 309         registers['h0A] <= 32'hXXXXXXXX;
 310         registers['h0B] <= 32'hXXXXXXXX;
 311         registers['h0C] <= 32'hXXXXXXXX;
 312         registers['h0D] <= 32'hXXXXXXXX;
 313         registers['h0E] <= 32'hXXXXXXXX;
 314         registers['h0F] <= 32'hXXXXXXXX;
 315         registers['h10] <= 32'hXXXXXXXX;
 316         registers['h11] <= 32'hXXXXXXXX;
 317         registers['h12] <= 32'hXXXXXXXX;
 318         registers['h13] <= 32'hXXXXXXXX;
 319         registers['h14] <= 32'hXXXXXXXX;
 320         registers['h15] <= 32'hXXXXXXXX;
 321         registers['h16] <= 32'hXXXXXXXX;
 322         registers['h17] <= 32'hXXXXXXXX;
 323         registers['h18] <= 32'hXXXXXXXX;
 324         registers['h19] <= 32'hXXXXXXXX;
 325         registers['h1A] <= 32'hXXXXXXXX;
 326         registers['h1B] <= 32'hXXXXXXXX;
 327         registers['h1C] <= 32'hXXXXXXXX;
 328         registers['h1D] <= 32'hXXXXXXXX;
 329         registers['h1E] <= 32'hXXXXXXXX;
 330         registers['h1F] <= 32'hXXXXXXXX;
 331     end
 332     endtask
 333
 334     task write_register(input [4:0] register_number, input [31:0] value);
 335     begin
 336         if(register_number != 0)
 337             registers[register_number] <= value;
 338     end
 339     endtask
 340
 341     function [31:0] evaluate_csr_funct3_operation(input [2:0] funct3, input [31:0] previous_value, input [31:0] written_value);
 342     begin
 343         case(funct3)
 344         `funct3_csrrw, `funct3_csrrwi:
 345             evaluate_csr_funct3_operation = written_value;
 346         `funct3_csrrs, `funct3_csrrsi:
 347             evaluate_csr_funct3_operation = written_value | previous_value;
 348         `funct3_csrrc, `funct3_csrrci:
 349             evaluate_csr_funct3_operation = ~written_value & previous_value;
 350         default:
 351             evaluate_csr_funct3_operation = 32'hXXXXXXXX;
 352         endcase
 353     end
 354     endfunction
 355
 356     parameter misa_a = 1'b0;
 357     parameter misa_b = 1'b0;
 358     parameter misa_c = 1'b0;
 359     parameter misa_d = 1'b0;
 360     parameter misa_e = 1'b0;
 361     parameter misa_f = 1'b0;
 362     parameter misa_g = 1'b0;
 363     parameter misa_h = 1'b0;
 364     parameter misa_i = 1'b1;
 365     parameter misa_j = 1'b0;
 366     parameter misa_k = 1'b0;
 367     parameter misa_l = 1'b0;
 368     parameter misa_m = 1'b0;
 369     parameter misa_n = 1'b0;
 370     parameter misa_o = 1'b0;
 371     parameter misa_p = 1'b0;
 372     parameter misa_q = 1'b0;
 373     parameter misa_r = 1'b0;
 374     parameter misa_s = 1'b0;
 375     parameter misa_t = 1'b0;
 376     parameter misa_u = 1'b0;
 377     parameter misa_v = 1'b0;
 378     parameter misa_w = 1'b0;
 379     parameter misa_x = 1'b0;
 380     parameter misa_y = 1'b0;
 381     parameter misa_z = 1'b0;
 382     parameter misa = {
 383         2'b01,
 384         4'b0,
 385         misa_z,
 386         misa_y,
 387         misa_x,
 388         misa_w,
 389         misa_v,
 390         misa_u,
 391         misa_t,
 392         misa_s,
 393         misa_r,
 394         misa_q,
 395         misa_p,
 396         misa_o,
 397         misa_n,
 398         misa_m,
 399         misa_l,
 400         misa_k,
 401         misa_j,
 402         misa_i,
 403         misa_h,
 404         misa_g,
 405         misa_f,
 406         misa_e,
 407         misa_d,
 408         misa_c,
 409         misa_b,
 410         misa_a};
 411
 412     parameter mvendorid = 32'b0;
 413     parameter marchid = 32'b0;
 414     parameter mimpid = 32'b0;
 415     parameter mhartid = 32'b0;
 416
 417     function [31:0] make_mstatus(input mstatus_tsr,
 418         input mstatus_tw,
 419         input mstatus_tvm,
 420         input mstatus_mxr,
 421         input mstatus_sum,
 422         input mstatus_mprv,
 423         input [1:0] mstatus_xs,
 424         input [1:0] mstatus_fs,
 425         input [1:0] mstatus_mpp,
 426         input mstatus_spp,
 427         input mstatus_mpie,
 428         input mstatus_spie,
 429         input mstatus_upie,
 430         input mstatus_mie,
 431         input mstatus_sie,
 432         input mstatus_uie);
 433     begin
 434         make_mstatus = {(mstatus_xs == 2'b11) | (mstatus_fs == 2'b11),
 435             8'b0,
 436             mstatus_tsr,
 437             mstatus_tw,
 438             mstatus_tvm,
 439             mstatus_mxr,
 440             mstatus_sum,
 441             mstatus_mprv,
 442             mstatus_xs,
 443             mstatus_fs,
 444             mstatus_mpp,
 445             2'b0,
 446             mstatus_spp,
 447             mstatus_mpie,
 448             1'b0,
 449             mstatus_spie,
 450             mstatus_upie,
 451             mstatus_mie,
 452             1'b0,
 453             mstatus_sie,
 454             mstatus_uie};
 455     end
 456     endfunction
 457
 458     wire mip_meip = 0; // TODO: implement external interrupts
 459     parameter mip_seip = 0;
 460     parameter mip_ueip = 0;
 461     wire mip_mtip = 0; // TODO: implement timer interrupts
 462     parameter mip_stip = 0;
 463     parameter mip_utip = 0;
 464     parameter mip_msip = 0;
 465     parameter mip_ssip = 0;
 466     parameter mip_usip = 0;
 467
 468     wire csr_op_is_valid;
 469
 470     function `fetch_action get_fetch_action(
 471         input `fetch_output_state fetch_output_state,
 472         input `decode_action decode_action,
 473         input load_store_misaligned,
 474         input memory_interface_rw_address_valid,
 475         input memory_interface_rw_wait,
 476         input branch_taken,
 477         input misaligned_jump_target,
 478         input csr_op_is_valid
 479         );
 480     begin
 481         case(fetch_output_state)
 482         `fetch_output_state_empty:
 483             get_fetch_action = `fetch_action_default;
 484         `fetch_output_state_trap:
 485             get_fetch_action = `fetch_action_ack_trap;
 486         `fetch_output_state_valid: begin
 487             if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 488                 get_fetch_action = `fetch_action_error_trap;
 489             end
 490             else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 491                 get_fetch_action = `fetch_action_noerror_trap;
 492             end
 493             else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
 494                 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
 495                     get_fetch_action = `fetch_action_error_trap;
 496                 end
 497                 else if(memory_interface_rw_wait) begin
 498                     get_fetch_action = `fetch_action_wait;
 499                 end
 500                 else begin
 501                     get_fetch_action = `fetch_action_default;
 502                 end
 503             end
 504             else if((decode_action & `decode_action_fence_i) != 0) begin
 505                 get_fetch_action = `fetch_action_fence;
 506             end
 507             else if((decode_action & `decode_action_branch) != 0) begin
 508                 if(branch_taken) begin
 509                     if(misaligned_jump_target) begin
 510                         get_fetch_action = `fetch_action_error_trap;
 511                     end
 512                     else begin
 513                         get_fetch_action = `fetch_action_jump;
 514                     end
 515                 end
 516                 else
 517                 begin
 518                     get_fetch_action = `fetch_action_default;
 519                 end
 520             end
 521             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 522                 if(misaligned_jump_target) begin
 523                     get_fetch_action = `fetch_action_error_trap;
 524                 end
 525                 else begin
 526                     get_fetch_action = `fetch_action_jump;
 527                 end
 528             end
 529             else if((decode_action & `decode_action_csr) != 0) begin
 530                 if(csr_op_is_valid)
 531                     get_fetch_action = `fetch_action_default;
 532                 else
 533                     get_fetch_action = `fetch_action_error_trap;
 534             end
 535             else begin
 536                 get_fetch_action = `fetch_action_default;
 537             end
 538         end
 539         default:
 540             get_fetch_action = 32'hXXXXXXXX;
 541         endcase
 542     end
 543     endfunction
 544
 545     assign fetch_action = get_fetch_action(
 546         fetch_output_state,
 547         decode_action,
 548         load_store_misaligned,
 549         memory_interface_rw_address_valid,
 550         memory_interface_rw_wait,
 551         branch_taken,
 552         misaligned_jump_target,
 553         csr_op_is_valid
 554         );
 555
 556     task handle_trap;
 557     begin
 558         mstatus_mpie = mstatus_mie;
 559         mstatus_mie = 0;
 560         mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
 561         if(fetch_action == `fetch_action_ack_trap) begin
 562             mcause = `cause_instruction_access_fault;
 563         end
 564         else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 565             mcause = `cause_illegal_instruction;
 566         end
 567         else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 568             mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
 569         end
 570         else if((decode_action & `decode_action_load) != 0) begin
 571             if(load_store_misaligned)
 572                 mcause = `cause_load_address_misaligned;
 573             else
 574                 mcause = `cause_load_access_fault;
 575         end
 576         else if((decode_action & `decode_action_store) != 0) begin
 577             if(load_store_misaligned)
 578                 mcause = `cause_store_amo_address_misaligned;
 579             else
 580                 mcause = `cause_store_amo_access_fault;
 581         end
 582         else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
 583             mcause = `cause_instruction_address_misaligned;
 584         end
 585         else begin
 586             mcause = `cause_illegal_instruction;
 587         end
 588     end
 589     endtask
 590
 591     wire [11:0] csr_number = decoder_immediate;
 592     wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
 593     wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
 594     wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
 595
 596     function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
 597     begin
 598         case(csr_number)
 599         `csr_ustatus,
 600         `csr_fflags,
 601         `csr_frm,
 602         `csr_fcsr,
 603         `csr_uie,
 604         `csr_utvec,
 605         `csr_uscratch,
 606         `csr_uepc,
 607         `csr_ucause,
 608         `csr_utval,
 609         `csr_uip,
 610         `csr_sstatus,
 611         `csr_sedeleg,
 612         `csr_sideleg,
 613         `csr_sie,
 614         `csr_stvec,
 615         `csr_scounteren,
 616         `csr_sscratch,
 617         `csr_sepc,
 618         `csr_scause,
 619         `csr_stval,
 620         `csr_sip,
 621         `csr_satp,
 622         `csr_medeleg,
 623         `csr_mideleg,
 624         `csr_dcsr,
 625         `csr_dpc,
 626         `csr_dscratch:
 627             get_csr_op_is_valid = 0;
 628         `csr_cycle,
 629         `csr_time,
 630         `csr_instret,
 631         `csr_cycleh,
 632         `csr_timeh,
 633         `csr_instreth,
 634         `csr_mvendorid,
 635         `csr_marchid,
 636         `csr_mimpid,
 637         `csr_mhartid:
 638             get_csr_op_is_valid = ~csr_writes;
 639         `csr_misa,
 640         `csr_mstatus,
 641         `csr_mie,
 642         `csr_mtvec,
 643         `csr_mscratch,
 644         `csr_mepc,
 645         `csr_mcause,
 646         `csr_mip:
 647             get_csr_op_is_valid = 1;
 648         `csr_mcounteren,
 649         `csr_mtval,
 650         `csr_mcycle,
 651         `csr_minstret,
 652         `csr_mcycleh,
 653         `csr_minstreth:
 654             // TODO: CSRs not implemented yet
 655             get_csr_op_is_valid = 0;
 656         endcase
 657     end
 658     endfunction
 659
 660     assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
 661
 662     wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
 663     wire [63:0] time_counter = 0; // TODO: implement time_counter
 664     wire [63:0] instret_counter = 0; // TODO: implement instret_counter
 665
 666     always @(posedge clk) begin:main_block
 667         if(reset) begin
 668             reset_to_initial();
 669             disable main_block;
 670         end
 671         case(fetch_output_state)
 672         `fetch_output_state_empty: begin
 673         end
 674         `fetch_output_state_trap: begin
 675             handle_trap();
 676         end
 677         `fetch_output_state_valid: begin:valid
 678             if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
 679                 handle_trap();
 680             end
 681             else if((decode_action & `decode_action_load) != 0) begin
 682                 if(~memory_interface_rw_wait)
 683                     write_register(decoder_rd, loaded_value);
 684             end
 685             else if((decode_action & `decode_action_op_op_imm) != 0) begin
 686                 write_register(decoder_rd, alu_result);
 687             end
 688             else if((decode_action & `decode_action_lui_auipc) != 0) begin
 689                 write_register(decoder_rd, lui_auipc_result);
 690             end
 691             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 692                 write_register(decoder_rd, fetch_output_pc + 4);
 693             end
 694             else if((decode_action & `decode_action_csr) != 0) begin:csr
 695                 reg [31:0] csr_output_value;
 696                 reg [31:0] csr_written_value;
 697                 csr_output_value = 32'hXXXXXXXX;
 698                 csr_written_value = 32'hXXXXXXXX;
 699                 case(csr_number)
 700                 `csr_cycle: begin
 701                     csr_output_value = cycle_counter[31:0];
 702                 end
 703                 `csr_time: begin
 704                     csr_output_value = time_counter[31:0];
 705                 end
 706                 `csr_instret: begin
 707                     csr_output_value = instret_counter[31:0];
 708                 end
 709                 `csr_cycleh: begin
 710                     csr_output_value = cycle_counter[63:32];
 711                 end
 712                 `csr_timeh: begin
 713                     csr_output_value = time_counter[63:32];
 714                 end
 715                 `csr_instreth: begin
 716                     csr_output_value = instret_counter[63:32];
 717                 end
 718                 `csr_mvendorid: begin
 719                     csr_output_value = mvendorid;
 720                 end
 721                 `csr_marchid: begin
 722                     csr_output_value = marchid;
 723                 end
 724                 `csr_mimpid: begin
 725                     csr_output_value = mimpid;
 726                 end
 727                 `csr_mhartid: begin
 728                     csr_output_value = mhartid;
 729                 end
 730                 `csr_misa: begin
 731                     csr_output_value = misa;
 732                 end
 733                 `csr_mstatus: begin
 734                     csr_output_value = make_mstatus(mstatus_tsr,
 735                                                     mstatus_tw,
 736                                                     mstatus_tvm,
 737                                                     mstatus_mxr,
 738                                                     mstatus_sum,
 739                                                     mstatus_mprv,
 740                                                     mstatus_xs,
 741                                                     mstatus_fs,
 742                                                     mstatus_mpp,
 743                                                     mstatus_spp,
 744                                                     mstatus_mpie,
 745                                                     mstatus_spie,
 746                                                     mstatus_upie,
 747                                                     mstatus_mie,
 748                                                     mstatus_sie,
 749                                                     mstatus_uie);
 750                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 751                     if(csr_writes) begin
 752                         mstatus_mpie = csr_written_value[7];
 753                         mstatus_mie = csr_written_value[3];
 754                     end
 755                 end
 756                 `csr_mie: begin
 757                     csr_output_value = 0;
 758                     csr_output_value[11] = mie_meie;
 759                     csr_output_value[9] = mie_seie;
 760                     csr_output_value[8] = mie_ueie;
 761                     csr_output_value[7] = mie_mtie;
 762                     csr_output_value[5] = mie_stie;
 763                     csr_output_value[4] = mie_utie;
 764                     csr_output_value[3] = mie_msie;
 765                     csr_output_value[1] = mie_ssie;
 766                     csr_output_value[0] = mie_usie;
 767                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 768                     if(csr_writes) begin
 769                         mie_meie = csr_written_value[11];
 770                         mie_mtie = csr_written_value[7];
 771                         mie_msie = csr_written_value[3];
 772                     end
 773                 end
 774                 `csr_mtvec: begin
 775                     csr_output_value = mtvec;
 776                 end
 777                 `csr_mscratch: begin
 778                     csr_output_value = mscratch;
 779                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 780                     if(csr_writes)
 781                         mscratch = csr_written_value;
 782                 end
 783                 `csr_mepc: begin
 784                     csr_output_value = mepc;
 785                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 786                     if(csr_writes)
 787                         mepc = csr_written_value;
 788                 end
 789                 `csr_mcause: begin
 790                     csr_output_value = mcause;
 791                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 792                     if(csr_writes)
 793                         mcause = csr_written_value;
 794                 end
 795                 `csr_mip: begin
 796                     csr_output_value = 0;
 797                     csr_output_value[11] = mip_meip;
 798                     csr_output_value[9] = mip_seip;
 799                     csr_output_value[8] = mip_ueip;
 800                     csr_output_value[7] = mip_mtip;
 801                     csr_output_value[5] = mip_stip;
 802                     csr_output_value[4] = mip_utip;
 803                     csr_output_value[3] = mip_msip;
 804                     csr_output_value[1] = mip_ssip;
 805                     csr_output_value[0] = mip_usip;
 806                 end
 807                 endcase
 808                 if(csr_reads)
 809                     write_register(decoder_rd, csr_output_value);
 810             end
 811             else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
 812                 // do nothing
 813             end
 814         end
 815         endcase
 816     end
 817
 818 endmodule
 819 """
 820