cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 import string
  30 from migen import *
  31 from migen.fhdl import verilog
  32 from migen.fhdl.structure import _Operator
  33
  34 from riscvdefs import *
  35 from cpudefs import *
  36
  37 class MemoryInterface:
  38     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  39     fetch_data = Signal(32, name="memory_interface_fetch_data")
  40     fetch_valid = Signal(name="memory_interface_fetch_valid")
  41     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  42     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  43     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  44     rw_active = Signal(name="memory_interface_rw_active")
  45     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  46     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  47     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  48     rw_wait = Signal(name="memory_interface_rw_wait")
  49
  50
  51 class Decoder:
  52     funct7 = Signal(7, name="decoder_funct7")
  53     funct3 = Signal(3, name="decoder_funct3")
  54     rd = Signal(5, name="decoder_rd")
  55     rs1 = Signal(5, name="decoder_rs1")
  56     rs2 = Signal(5, name="decoder_rs2")
  57     immediate = Signal(32, name="decoder_immediate")
  58     opcode = Signal(7, name="decoder_opcode")
  59     act = Signal(decode_action, name="decoder_action")
  60
  61 class MStatus:
  62     def __init__(self, comb, sync):
  63         self.comb = comb
  64         self.sync = sync
  65         self.mpie = Signal(name="mstatus_mpie")
  66         self.mie = Signal(name="mstatus_mie")
  67         self.mprv = Signal(name="mstatus_mprv")
  68         self.tsr = Signal(name="mstatus_tsr")
  69         self.tw = Signal(name="mstatus_tw")
  70         self.tvm = Signal(name="mstatus_tvm")
  71         self.mxr = Signal(name="mstatus_mxr")
  72         self._sum = Signal(name="mstatus_sum")
  73         self.xs = Signal(name="mstatus_xs")
  74         self.fs = Signal(name="mstatus_fs")
  75         self.mpp = Signal(2, name="mstatus_mpp")
  76         self.spp = Signal(name="mstatus_spp")
  77         self.spie = Signal(name="mstatus_spie")
  78         self.upie = Signal(name="mstatus_upie")
  79         self.sie = Signal(name="mstatus_sie")
  80         self.uie = Signal(name="mstatus_uie")
  81
  82         for n in dir(self):
  83             if n in ['make', 'mpp', 'comb', 'sync'] or n.startswith("_"):
  84                 continue
  85             self.comb += getattr(self, n).eq(0x0)
  86         self.comb += self.mpp.eq(0b11)
  87
  88         self.sync += self.mie.eq(0)
  89         self.sync += self.mpie.eq(0)
  90
  91     def make(self):
  92         return Cat(
  93                 self.uie, self.sie, Constant(0), self.mie,
  94                 self.upie, self.spie, Constant(0), self.mpie,
  95                 self.spp, Constant(0, 2), self.mpp,
  96                 self.fs, self.xs, self.mprv, self._sum,
  97                 self.mxr, self.tvm, self.tw, self.tsr,
  98                 Constant(0, 8),
  99                 (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2))
 100                 )
 101
 102
 103 class MIE:
 104     def __init__(self, comb, sync):
 105         self.comb = comb
 106         self.sync = sync
 107         self.meie = Signal(name="mie_meie")
 108         self.mtie = Signal(name="mie_mtie")
 109         self.msie = Signal(name="mie_msie")
 110         self.ueie = Signal(name="mie_ueie")
 111         self.stie = Signal(name="mie_stie")
 112         self.utie = Signal(name="mie_utie")
 113         self.ssie = Signal(name="mie_ssie")
 114         self.usie = Signal(name="mie_usie")
 115
 116         for n in dir(self):
 117             if n in ['make', 'comb', 'sync'] or n.startswith("_"):
 118                 continue
 119             self.comb += getattr(self, n).eq(0x0)
 120
 121         self.sync += self.meie.eq(0)
 122         self.sync += self.mtie.eq(0)
 123         self.sync += self.msie.eq(0)
 124
 125 class MIP:
 126     def __init__(self, comb, sync):
 127         self.comb = comb
 128         self.sync = sync
 129         self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts
 130         self.seip = Signal(name="mip_seip")
 131         self.ueip = Signal(name="mip_uiep")
 132         self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts
 133         self.stip = Signal(name="mip_stip")
 134         self.msip = Signal(name="mip_stip")
 135         self.utip = Signal(name="mip_utip")
 136         self.ssip = Signal(name="mip_ssip")
 137         self.usip = Signal(name="mip_usip")
 138
 139         for n in dir(self):
 140             if n in ['comb', 'sync'] or n.startswith("_"):
 141                 continue
 142             self.comb += getattr(self, n).eq(0x0)
 143
 144
 145 class M:
 146     def __init__(self, comb, sync):
 147         self.comb = comb
 148         self.sync = sync
 149         self.mcause = Signal(32)
 150         self.mepc = Signal(32)
 151         self.mscratch = Signal(32)
 152         self.sync += self.mcause.eq(0)
 153         self.sync += self.mepc.eq(0) # 32'hXXXXXXXX;
 154         self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
 155
 156 class Misa:
 157
 158     def __init__(self, comb, sync):
 159         self.comb = comb
 160         self.sync = sync
 161         self.misa = Signal(32)
 162         cl = []
 163         for l in list(string.ascii_lowercase):
 164             value = 1 if l == 'i' else 0
 165             cl.append(Constant(value))
 166         cl.append(Constant(0, 4))
 167         cl.append(Constant(0b01, 2))
 168         self.comb += self.misa.eq(Cat(cl))
 169
 170
 171 class CPU(Module):
 172     """
 173     """
 174
 175     def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
 176         return Case(funct3[:2],
 177                 { F3.sb: ls.eq(Constant(0)),
 178                   F3.sh: ls.eq(load_store_address_low_2[0] != 0),
 179                   F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
 180                   "default": ls.eq(Constant(1))
 181                 })
 182
 183     def get_lsbm(self, dc):
 184         return Cat(Constant(1),
 185                    Mux((dc.funct3[1] | dc.funct3[0]),
 186                        Constant(1), Constant(0)),
 187                    Mux((dc.funct3[1]),
 188                        Constant(0b11, 2), Constant(0, 2)))
 189
 190     # XXX this happens to get done by various self.sync actions
 191     #def reset_to_initial(self, m, mstatus, mie, registers):
 192     #    return [m.mcause.eq(0),
 193     #            ]
 194
 195     def write_register(self, register_number, value):
 196         return If(register_number != 0,
 197                   self.registers[register_number].eq(value)
 198                )
 199
 200     def evaluate_csr_funct3_op(self, funct3, previous_value, written_value):
 201         c = { "default": Constant(0, 32)}
 202         for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value
 203         for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value
 204         for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
 205         return Case(funct3, c)
 206
 207     """
 208     def get_fetch_action(self, fetch_output_state,
 209         input `decode_action decode_action,
 210         input load_store_misaligned,
 211         input memory_interface_rw_address_valid,
 212         input memory_interface_rw_wait,
 213         input branch_taken,
 214         input misaligned_jump_target,
 215         input csr_op_is_valid
 216         );
 217     begin
 218         case(fetch_output_state)
 219         `fetch_output_state_empty:
 220             get_fetch_action = `fetch_action_default;
 221         `fetch_output_state_trap:
 222             get_fetch_action = `fetch_action_ack_trap;
 223         `fetch_output_state_valid: begin
 224             if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 225                 get_fetch_action = `fetch_action_error_trap;
 226             end
 227             else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 228                 get_fetch_action = `fetch_action_noerror_trap;
 229             end
 230             else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
 231                 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
 232                     get_fetch_action = `fetch_action_error_trap;
 233                 end
 234                 else if(memory_interface_rw_wait) begin
 235                     get_fetch_action = `fetch_action_wait;
 236                 end
 237                 else begin
 238                     get_fetch_action = `fetch_action_default;
 239                 end
 240             end
 241             else if((decode_action & `decode_action_fence_i) != 0) begin
 242                 get_fetch_action = `fetch_action_fence;
 243             end
 244             else if((decode_action & `decode_action_branch) != 0) begin
 245                 if(branch_taken) begin
 246                     if(misaligned_jump_target) begin
 247                         get_fetch_action = `fetch_action_error_trap;
 248                     end
 249                     else begin
 250                         get_fetch_action = `fetch_action_jump;
 251                     end
 252                 end
 253                 else
 254                 begin
 255                     get_fetch_action = `fetch_action_default;
 256                 end
 257             end
 258             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 259                 if(misaligned_jump_target) begin
 260                     get_fetch_action = `fetch_action_error_trap;
 261                 end
 262                 else begin
 263                     get_fetch_action = `fetch_action_jump;
 264                 end
 265             end
 266             else if((decode_action & `decode_action_csr) != 0) begin
 267                 if(csr_op_is_valid)
 268                     get_fetch_action = `fetch_action_default;
 269                 else
 270                     get_fetch_action = `fetch_action_error_trap;
 271             end
 272             else begin
 273                 get_fetch_action = `fetch_action_default;
 274             end
 275         end
 276         default:
 277             get_fetch_action = 32'hXXXXXXXX;
 278         endcase
 279     end
 280     endfunction
 281     """
 282
 283     def __init__(self):
 284         self.clk = ClockSignal()
 285         self.reset = ResetSignal()
 286         self.tty_write = Signal()
 287         self.tty_write_data = Signal(8)
 288         self.tty_write_busy = Signal()
 289         self.switch_2 = Signal()
 290         self.switch_3 = Signal()
 291         self.led_1 = Signal()
 292         self.led_3 = Signal()
 293
 294         ram_size = Constant(0x8000)
 295         ram_start = Constant(0x10000, 32)
 296         reset_vector = Signal(32)
 297         mtvec = Signal(32)
 298
 299         reset_vector.eq(ram_start)
 300         mtvec.eq(ram_start + 0x40)
 301
 302         l = []
 303         for i in range(31):
 304             r = Signal(32, name="register%d" % i)
 305             l.append(r)
 306             self.sync += r.eq(Constant(0, 32))
 307         self.registers = Array(l)
 308
 309         mi = MemoryInterface()
 310
 311         mii = Instance("cpu_memory_interface", name="memory_instance",
 312                     p_ram_size = ram_size,
 313                     p_ram_start = ram_start,
 314                     i_clk=ClockSignal(),
 315                     i_rst=ResetSignal(),
 316                     i_fetch_address = mi.fetch_address,
 317                     o_fetch_data = mi.fetch_data,
 318                     o_fetch_valid = mi.fetch_valid,
 319                     i_rw_address = mi.rw_address,
 320                     i_rw_byte_mask = mi.rw_byte_mask,
 321                     i_rw_read_not_write = mi.rw_read_not_write,
 322                     i_rw_active = mi.rw_active,
 323                     i_rw_data_in = mi.rw_data_in,
 324                     o_rw_data_out = mi.rw_data_out,
 325                     o_rw_address_valid = mi.rw_address_valid,
 326                     o_rw_wait = mi.rw_wait,
 327                     o_tty_write = self.tty_write,
 328                     o_tty_write_data = self.tty_write_data,
 329                     i_tty_write_busy = self.tty_write_busy,
 330                     i_switch_2 = self.switch_2,
 331                     i_switch_3 = self.switch_3,
 332                     o_led_1 = self.led_1,
 333                     o_led_3 = self.led_3
 334                   )
 335         self.specials += mii
 336
 337         fetch_act = Signal(fetch_action)
 338         fetch_target_pc = Signal(32)
 339         fetch_output_pc = Signal(32)
 340         fetch_output_instruction = Signal(32)
 341         fetch_output_st = Signal(fetch_output_state)
 342
 343         fs = Instance("CPUFetchStage", name="fetch_stage",
 344             i_clk=ClockSignal(),
 345             i_rst=ResetSignal(),
 346             o_memory_interface_fetch_address = mi.fetch_address,
 347             i_memory_interface_fetch_data = mi.fetch_data,
 348             i_memory_interface_fetch_valid = mi.fetch_valid,
 349             i_fetch_action = fetch_act,
 350             i_target_pc = fetch_target_pc,
 351             o_output_pc = fetch_output_pc,
 352             o_output_instruction = fetch_output_instruction,
 353             o_output_state = fetch_output_st,
 354             i_reset_vector = reset_vector,
 355             i_mtvec = mtvec,
 356         )
 357         self.specials += fs
 358
 359         dc = Decoder()
 360
 361         cd = Instance("CPUDecoder", name="decoder",
 362             i_instruction = fetch_output_instruction,
 363             o_funct7 = dc.funct7,
 364             o_funct3 = dc.funct3,
 365             o_rd = dc.rd,
 366             o_rs1 = dc.rs1,
 367             o_rs2 = dc.rs2,
 368             o_immediate = dc.immediate,
 369             o_opcode = dc.opcode,
 370             o_decode_action = dc.act
 371         )
 372         self.specials += cd
 373
 374         register_rs1 = Signal(32)
 375         register_rs2 = Signal(32)
 376         self.comb += If(dc.rs1 == 0,
 377                         register_rs1.eq(0)
 378                      ).Else(
 379                         register_rs1.eq(self.registers[dc.rs1-1]))
 380         self.comb += If(dc.rs2 == 0,
 381                         register_rs2.eq(0)
 382                      ).Else(
 383                         register_rs2.eq(self.registers[dc.rs2-1]))
 384
 385         load_store_address = Signal(32)
 386         load_store_address_low_2 = Signal(2)
 387
 388         self.comb += load_store_address.eq(dc.immediate + register_rs1)
 389         self.comb += load_store_address_low_2.eq(
 390                             dc.immediate[:2] + register_rs1[:2])
 391
 392         load_store_misaligned = Signal()
 393
 394         lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3,
 395                                      load_store_address_low_2)
 396         self.comb += lsa
 397
 398         # XXX rwaddr not 31:2 any more
 399         self.comb += mi.rw_address.eq(load_store_address[2:])
 400
 401         unshifted_load_store_byte_mask = Signal(4)
 402
 403         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc))
 404
 405         # XXX yuck.  this will cause migen simulation to fail
 406         # (however conversion to verilog works)
 407         self.comb += mi.rw_byte_mask.eq(
 408                 _Operator("<<", [unshifted_load_store_byte_mask,
 409                                         load_store_address_low_2]))
 410
 411         # XXX not obvious
 412         b3 = Mux(load_store_address_low_2[1],
 413                  Mux(load_store_address_low_2[0], register_rs2[0:8],
 414                                                   register_rs2[8:16]),
 415                  Mux(load_store_address_low_2[0], register_rs2[16:24],
 416                                                   register_rs2[24:32]))
 417         b2 = Mux(load_store_address_low_2[1], register_rs2[0:8],
 418                                               register_rs2[16:24])
 419         b1 = Mux(load_store_address_low_2[0], register_rs2[0:8],
 420                                               register_rs2[8:16])
 421         b0 = register_rs2[0:8]
 422
 423         self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
 424
 425         # XXX not obvious
 426         unmasked_loaded_value = Signal(32)
 427
 428         b0 = Mux(load_store_address_low_2[1],
 429                  Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
 430                                                   mi.rw_data_out[16:24]),
 431                  Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
 432                                                   mi.rw_data_out[0:8]))
 433         b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
 434                                               mi.rw_data_out[8:16])
 435         b23 = mi.rw_data_out[16:32]
 436
 437         self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
 438
 439         # XXX not obvious
 440         loaded_value = Signal(32)
 441
 442         b0 = unmasked_loaded_value[0:8]
 443         b1 = Mux(dc.funct3[0:2] == 0,
 444                 Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8),
 445                 unmasked_loaded_value[8:16])
 446         b2 = Mux(dc.funct3[1] == 0,
 447                 Replicate(~dc.funct3[2] &
 448                            Mux(dc.funct3[0], unmasked_loaded_value[15],
 449                                                   unmasked_loaded_value[7]),
 450                           16),
 451                 unmasked_loaded_value[16:32])
 452
 453         self.comb += loaded_value.eq(Cat(b0, b1, b2))
 454
 455         self.comb += mi.rw_active.eq(~self.reset
 456                         & (fetch_output_st == fetch_output_state_valid)
 457                         & ~load_store_misaligned
 458                         & ((dc.act & (DA.load | DA.store)) != 0))
 459
 460         self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
 461
 462         # alu
 463         alu_a = Signal(32)
 464         alu_b = Signal(32)
 465         alu_result = Signal(32)
 466
 467         self.comb += alu_a.eq(register_rs1)
 468         self.comb += alu_b.eq(Mux(dc.opcode[5],
 469                                   register_rs2,
 470                                   dc.immediate))
 471
 472         ali = Instance("cpu_alu", name="alu",
 473             i_funct7 = dc.funct7,
 474             i_funct3 = dc.funct3,
 475             i_opcode = dc.opcode,
 476             i_a = alu_a,
 477             i_b = alu_b,
 478             o_result = alu_result
 479         )
 480         self.specials += ali
 481
 482         lui_auipc_result = Signal(32)
 483         self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
 484                                              dc.immediate,
 485                                              dc.immediate + fetch_output_pc))
 486
 487         self.comb += fetch_target_pc.eq(Cat(0,
 488                     Mux(dc.opcode != OP.jalr,
 489                                 fetch_output_pc[1:32],
 490                                 register_rs1[1:32] + dc.immediate[1:32])))
 491
 492         misaligned_jump_target = Signal()
 493         self.comb += misaligned_jump_target.eq(fetch_target_pc[1])
 494
 495         branch_arg_a = Signal(32)
 496         branch_arg_b = Signal(32)
 497         self.comb += branch_arg_a.eq(Cat( register_rs1[0:31],
 498                                           register_rs1[31] ^ ~dc.funct3[1]))
 499         self.comb += branch_arg_b.eq(Cat( register_rs2[0:31],
 500                                           register_rs2[31] ^ ~dc.funct3[1]))
 501
 502         branch_taken = Signal()
 503         self.comb += branch_taken.eq(dc.funct3[0] ^
 504                                      Mux(dc.funct3[2],
 505                                          branch_arg_a < branch_arg_b,
 506                                          branch_arg_a == branch_arg_b))
 507
 508         m = M(self.comb, self.sync)
 509         mstatus = MStatus(self.comb, self.sync)
 510         mie = MIE(self.comb, self.sync)
 511
 512         misa = Misa(self.comb, self.sync)
 513
 514         mvendorid = Signal(32)
 515         marchid = Signal(32)
 516         mimpid = Signal(32)
 517         mhartid = Signal(32)
 518         self.comb += mvendorid.eq(Constant(0, 32))
 519         self.comb += marchid.eq(Constant(0, 32))
 520         self.comb += mimpid.eq(Constant(0, 32))
 521         self.comb += mhartid.eq(Constant(0, 32))
 522
 523         mip = MIP(self.comb, self.sync)
 524
 525         csr_op_is_valid = Signal()
 526
 527 if __name__ == "__main__":
 528     example = CPU()
 529     print(verilog.convert(example,
 530          {
 531            example.tty_write,
 532            example.tty_write_data,
 533            example.tty_write_busy,
 534            example.switch_2,
 535            example.switch_3,
 536            example.led_1,
 537            example.led_3,
 538            }))
 539
 540 """
 541
 542     function `fetch_action get_fetch_action(
 543         input `fetch_output_state fetch_output_state,
 544         input `decode_action decode_action,
 545         input load_store_misaligned,
 546         input memory_interface_rw_address_valid,
 547         input memory_interface_rw_wait,
 548         input branch_taken,
 549         input misaligned_jump_target,
 550         input csr_op_is_valid
 551         );
 552     begin
 553         case(fetch_output_state)
 554         `fetch_output_state_empty:
 555             get_fetch_action = `fetch_action_default;
 556         `fetch_output_state_trap:
 557             get_fetch_action = `fetch_action_ack_trap;
 558         `fetch_output_state_valid: begin
 559             if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 560                 get_fetch_action = `fetch_action_error_trap;
 561             end
 562             else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 563                 get_fetch_action = `fetch_action_noerror_trap;
 564             end
 565             else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
 566                 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
 567                     get_fetch_action = `fetch_action_error_trap;
 568                 end
 569                 else if(memory_interface_rw_wait) begin
 570                     get_fetch_action = `fetch_action_wait;
 571                 end
 572                 else begin
 573                     get_fetch_action = `fetch_action_default;
 574                 end
 575             end
 576             else if((decode_action & `decode_action_fence_i) != 0) begin
 577                 get_fetch_action = `fetch_action_fence;
 578             end
 579             else if((decode_action & `decode_action_branch) != 0) begin
 580                 if(branch_taken) begin
 581                     if(misaligned_jump_target) begin
 582                         get_fetch_action = `fetch_action_error_trap;
 583                     end
 584                     else begin
 585                         get_fetch_action = `fetch_action_jump;
 586                     end
 587                 end
 588                 else
 589                 begin
 590                     get_fetch_action = `fetch_action_default;
 591                 end
 592             end
 593             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 594                 if(misaligned_jump_target) begin
 595                     get_fetch_action = `fetch_action_error_trap;
 596                 end
 597                 else begin
 598                     get_fetch_action = `fetch_action_jump;
 599                 end
 600             end
 601             else if((decode_action & `decode_action_csr) != 0) begin
 602                 if(csr_op_is_valid)
 603                     get_fetch_action = `fetch_action_default;
 604                 else
 605                     get_fetch_action = `fetch_action_error_trap;
 606             end
 607             else begin
 608                 get_fetch_action = `fetch_action_default;
 609             end
 610         end
 611         default:
 612             get_fetch_action = 32'hXXXXXXXX;
 613         endcase
 614     end
 615     endfunction
 616
 617     assign fetch_action = get_fetch_action(
 618         fetch_output_state,
 619         decode_action,
 620         load_store_misaligned,
 621         memory_interface_rw_address_valid,
 622         memory_interface_rw_wait,
 623         branch_taken,
 624         misaligned_jump_target,
 625         csr_op_is_valid
 626         );
 627
 628     task handle_trap;
 629     begin
 630         mstatus_mpie = mstatus_mie;
 631         mstatus_mie = 0;
 632         mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
 633         if(fetch_action == `fetch_action_ack_trap) begin
 634             mcause = `cause_instruction_access_fault;
 635         end
 636         else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 637             mcause = `cause_illegal_instruction;
 638         end
 639         else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 640             mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
 641         end
 642         else if((decode_action & `decode_action_load) != 0) begin
 643             if(load_store_misaligned)
 644                 mcause = `cause_load_address_misaligned;
 645             else
 646                 mcause = `cause_load_access_fault;
 647         end
 648         else if((decode_action & `decode_action_store) != 0) begin
 649             if(load_store_misaligned)
 650                 mcause = `cause_store_amo_address_misaligned;
 651             else
 652                 mcause = `cause_store_amo_access_fault;
 653         end
 654         else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
 655             mcause = `cause_instruction_address_misaligned;
 656         end
 657         else begin
 658             mcause = `cause_illegal_instruction;
 659         end
 660     end
 661     endtask
 662
 663     wire [11:0] csr_number = decoder_immediate;
 664     wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
 665     wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
 666     wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
 667
 668     function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
 669     begin
 670         case(csr_number)
 671         `csr_ustatus,
 672         `csr_fflags,
 673         `csr_frm,
 674         `csr_fcsr,
 675         `csr_uie,
 676         `csr_utvec,
 677         `csr_uscratch,
 678         `csr_uepc,
 679         `csr_ucause,
 680         `csr_utval,
 681         `csr_uip,
 682         `csr_sstatus,
 683         `csr_sedeleg,
 684         `csr_sideleg,
 685         `csr_sie,
 686         `csr_stvec,
 687         `csr_scounteren,
 688         `csr_sscratch,
 689         `csr_sepc,
 690         `csr_scause,
 691         `csr_stval,
 692         `csr_sip,
 693         `csr_satp,
 694         `csr_medeleg,
 695         `csr_mideleg,
 696         `csr_dcsr,
 697         `csr_dpc,
 698         `csr_dscratch:
 699             get_csr_op_is_valid = 0;
 700         `csr_cycle,
 701         `csr_time,
 702         `csr_instret,
 703         `csr_cycleh,
 704         `csr_timeh,
 705         `csr_instreth,
 706         `csr_mvendorid,
 707         `csr_marchid,
 708         `csr_mimpid,
 709         `csr_mhartid:
 710             get_csr_op_is_valid = ~csr_writes;
 711         `csr_misa,
 712         `csr_mstatus,
 713         `csr_mie,
 714         `csr_mtvec,
 715         `csr_mscratch,
 716         `csr_mepc,
 717         `csr_mcause,
 718         `csr_mip:
 719             get_csr_op_is_valid = 1;
 720         `csr_mcounteren,
 721         `csr_mtval,
 722         `csr_mcycle,
 723         `csr_minstret,
 724         `csr_mcycleh,
 725         `csr_minstreth:
 726             // TODO: CSRs not implemented yet
 727             get_csr_op_is_valid = 0;
 728         endcase
 729     end
 730     endfunction
 731
 732     assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
 733
 734     wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
 735     wire [63:0] time_counter = 0; // TODO: implement time_counter
 736     wire [63:0] instret_counter = 0; // TODO: implement instret_counter
 737
 738     always @(posedge clk) begin:main_block
 739         if(reset) begin
 740             reset_to_initial();
 741             disable main_block;
 742         end
 743         case(fetch_output_state)
 744         `fetch_output_state_empty: begin
 745         end
 746         `fetch_output_state_trap: begin
 747             handle_trap();
 748         end
 749         `fetch_output_state_valid: begin:valid
 750             if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
 751                 handle_trap();
 752             end
 753             else if((decode_action & `decode_action_load) != 0) begin
 754                 if(~memory_interface_rw_wait)
 755                     write_register(decoder_rd, loaded_value);
 756             end
 757             else if((decode_action & `decode_action_op_op_imm) != 0) begin
 758                 write_register(decoder_rd, alu_result);
 759             end
 760             else if((decode_action & `decode_action_lui_auipc) != 0) begin
 761                 write_register(decoder_rd, lui_auipc_result);
 762             end
 763             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 764                 write_register(decoder_rd, fetch_output_pc + 4);
 765             end
 766             else if((decode_action & `decode_action_csr) != 0) begin:csr
 767                 reg [31:0] csr_output_value;
 768                 reg [31:0] csr_written_value;
 769                 csr_output_value = 32'hXXXXXXXX;
 770                 csr_written_value = 32'hXXXXXXXX;
 771                 case(csr_number)
 772                 `csr_cycle: begin
 773                     csr_output_value = cycle_counter[31:0];
 774                 end
 775                 `csr_time: begin
 776                     csr_output_value = time_counter[31:0];
 777                 end
 778                 `csr_instret: begin
 779                     csr_output_value = instret_counter[31:0];
 780                 end
 781                 `csr_cycleh: begin
 782                     csr_output_value = cycle_counter[63:32];
 783                 end
 784                 `csr_timeh: begin
 785                     csr_output_value = time_counter[63:32];
 786                 end
 787                 `csr_instreth: begin
 788                     csr_output_value = instret_counter[63:32];
 789                 end
 790                 `csr_mvendorid: begin
 791                     csr_output_value = mvendorid;
 792                 end
 793                 `csr_marchid: begin
 794                     csr_output_value = marchid;
 795                 end
 796                 `csr_mimpid: begin
 797                     csr_output_value = mimpid;
 798                 end
 799                 `csr_mhartid: begin
 800                     csr_output_value = mhartid;
 801                 end
 802                 `csr_misa: begin
 803                     csr_output_value = misa;
 804                 end
 805                 `csr_mstatus: begin
 806                     csr_output_value = make_mstatus(mstatus_tsr,
 807                                                     mstatus_tw,
 808                                                     mstatus_tvm,
 809                                                     mstatus_mxr,
 810                                                     mstatus_sum,
 811                                                     mstatus_mprv,
 812                                                     mstatus_xs,
 813                                                     mstatus_fs,
 814                                                     mstatus_mpp,
 815                                                     mstatus_spp,
 816                                                     mstatus_mpie,
 817                                                     mstatus_spie,
 818                                                     mstatus_upie,
 819                                                     mstatus_mie,
 820                                                     mstatus_sie,
 821                                                     mstatus_uie);
 822                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 823                     if(csr_writes) begin
 824                         mstatus_mpie = csr_written_value[7];
 825                         mstatus_mie = csr_written_value[3];
 826                     end
 827                 end
 828                 `csr_mie: begin
 829                     csr_output_value = 0;
 830                     csr_output_value[11] = mie_meie;
 831                     csr_output_value[9] = mie_seie;
 832                     csr_output_value[8] = mie_ueie;
 833                     csr_output_value[7] = mie_mtie;
 834                     csr_output_value[5] = mie_stie;
 835                     csr_output_value[4] = mie_utie;
 836                     csr_output_value[3] = mie_msie;
 837                     csr_output_value[1] = mie_ssie;
 838                     csr_output_value[0] = mie_usie;
 839                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 840                     if(csr_writes) begin
 841                         mie_meie = csr_written_value[11];
 842                         mie_mtie = csr_written_value[7];
 843                         mie_msie = csr_written_value[3];
 844                     end
 845                 end
 846                 `csr_mtvec: begin
 847                     csr_output_value = mtvec;
 848                 end
 849                 `csr_mscratch: begin
 850                     csr_output_value = mscratch;
 851                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 852                     if(csr_writes)
 853                         mscratch = csr_written_value;
 854                 end
 855                 `csr_mepc: begin
 856                     csr_output_value = mepc;
 857                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 858                     if(csr_writes)
 859                         mepc = csr_written_value;
 860                 end
 861                 `csr_mcause: begin
 862                     csr_output_value = mcause;
 863                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 864                     if(csr_writes)
 865                         mcause = csr_written_value;
 866                 end
 867                 `csr_mip: begin
 868                     csr_output_value = 0;
 869                     csr_output_value[11] = mip_meip;
 870                     csr_output_value[9] = mip_seip;
 871                     csr_output_value[8] = mip_ueip;
 872                     csr_output_value[7] = mip_mtip;
 873                     csr_output_value[5] = mip_stip;
 874                     csr_output_value[4] = mip_utip;
 875                     csr_output_value[3] = mip_msip;
 876                     csr_output_value[1] = mip_ssip;
 877                     csr_output_value[0] = mip_usip;
 878                 end
 879                 endcase
 880                 if(csr_reads)
 881                     write_register(decoder_rd, csr_output_value);
 882             end
 883             else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
 884                 // do nothing
 885             end
 886         end
 887         endcase
 888     end
 889
 890 endmodule
 891 """
 892