cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 import string
  30 from migen import *
  31 from migen.fhdl import verilog
  32 from migen.fhdl.structure import _Operator
  33
  34 from riscvdefs import *
  35 from cpudefs import *
  36
  37 class MemoryInterface:
  38     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  39     fetch_data = Signal(32, name="memory_interface_fetch_data")
  40     fetch_valid = Signal(name="memory_interface_fetch_valid")
  41     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  42     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  43     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  44     rw_active = Signal(name="memory_interface_rw_active")
  45     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  46     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  47     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  48     rw_wait = Signal(name="memory_interface_rw_wait")
  49
  50
  51 class Decoder:
  52     funct7 = Signal(7, name="decoder_funct7")
  53     funct3 = Signal(3, name="decoder_funct3")
  54     rd = Signal(5, name="decoder_rd")
  55     rs1 = Signal(5, name="decoder_rs1")
  56     rs2 = Signal(5, name="decoder_rs2")
  57     immediate = Signal(32, name="decoder_immediate")
  58     opcode = Signal(7, name="decoder_opcode")
  59     act = Signal(decode_action, name="decoder_action")
  60
  61 class MStatus:
  62     def __init__(self, comb, sync):
  63         self.comb = comb
  64         self.sync = sync
  65         self.mpie = Signal(name="mstatus_mpie")
  66         self.mie = Signal(name="mstatus_mie")
  67         self.mprv = Signal(name="mstatus_mprv")
  68         self.tsr = Signal(name="mstatus_tsr")
  69         self.tw = Signal(name="mstatus_tw")
  70         self.tvm = Signal(name="mstatus_tvm")
  71         self.mxr = Signal(name="mstatus_mxr")
  72         self._sum = Signal(name="mstatus_sum")
  73         self.xs = Signal(name="mstatus_xs")
  74         self.fs = Signal(name="mstatus_fs")
  75         self.mpp = Signal(2, name="mstatus_mpp")
  76         self.spp = Signal(name="mstatus_spp")
  77         self.spie = Signal(name="mstatus_spie")
  78         self.upie = Signal(name="mstatus_upie")
  79         self.sie = Signal(name="mstatus_sie")
  80         self.uie = Signal(name="mstatus_uie")
  81
  82         for n in dir(self):
  83             if n in ['make', 'mpp', 'comb', 'sync'] or n.startswith("_"):
  84                 continue
  85             self.comb += getattr(self, n).eq(0x0)
  86         self.comb += self.mpp.eq(0b11)
  87
  88         self.sync += self.mie.eq(0)
  89         self.sync += self.mpie.eq(0)
  90
  91     def make(self):
  92         return Cat(
  93                 self.uie, self.sie, Constant(0), self.mie,
  94                 self.upie, self.spie, Constant(0), self.mpie,
  95                 self.spp, Constant(0, 2), self.mpp,
  96                 self.fs, self.xs, self.mprv, self._sum,
  97                 self.mxr, self.tvm, self.tw, self.tsr,
  98                 Constant(0, 8),
  99                 (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2))
 100                 )
 101
 102
 103 class MIE:
 104     def __init__(self, comb, sync):
 105         self.comb = comb
 106         self.sync = sync
 107         self.meie = Signal(name="mie_meie")
 108         self.mtie = Signal(name="mie_mtie")
 109         self.msie = Signal(name="mie_msie")
 110         self.ueie = Signal(name="mie_ueie")
 111         self.stie = Signal(name="mie_stie")
 112         self.utie = Signal(name="mie_utie")
 113         self.ssie = Signal(name="mie_ssie")
 114         self.usie = Signal(name="mie_usie")
 115
 116         for n in dir(self):
 117             if n in ['make', 'comb', 'sync'] or n.startswith("_"):
 118                 continue
 119             self.comb += getattr(self, n).eq(0x0)
 120
 121         self.sync += self.meie.eq(0)
 122         self.sync += self.mtie.eq(0)
 123         self.sync += self.msie.eq(0)
 124
 125 class MIP:
 126     def __init__(self, comb, sync):
 127         self.comb = comb
 128         self.sync = sync
 129         self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts
 130         self.seip = Signal(name="mip_seip")
 131         self.ueip = Signal(name="mip_uiep")
 132         self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts
 133         self.stip = Signal(name="mip_stip")
 134         self.msip = Signal(name="mip_stip")
 135         self.utip = Signal(name="mip_utip")
 136         self.ssip = Signal(name="mip_ssip")
 137         self.usip = Signal(name="mip_usip")
 138
 139         for n in dir(self):
 140             if n in ['comb', 'sync'] or n.startswith("_"):
 141                 continue
 142             self.comb += getattr(self, n).eq(0x0)
 143
 144
 145 class M:
 146     def __init__(self, comb, sync):
 147         self.comb = comb
 148         self.sync = sync
 149         self.mcause = Signal(32)
 150         self.mepc = Signal(32)
 151         self.mscratch = Signal(32)
 152         self.sync += self.mcause.eq(0)
 153         self.sync += self.mepc.eq(0) # 32'hXXXXXXXX;
 154         self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
 155
 156
 157 class Misa:
 158     def __init__(self, comb, sync):
 159         self.comb = comb
 160         self.sync = sync
 161         self.misa = Signal(32)
 162         cl = []
 163         for l in list(string.ascii_lowercase):
 164             value = 1 if l == 'i' else 0
 165             cl.append(Constant(value))
 166         cl.append(Constant(0, 4))
 167         cl.append(Constant(0b01, 2))
 168         self.comb += self.misa.eq(Cat(cl))
 169
 170
 171 class Fetch:
 172     def __init__(self, comb, sync):
 173         self.comb = comb
 174         self.sync = sync
 175         self.action = Signal(fetch_action, name="fetch_action")
 176         self.target_pc = Signal(32, name="fetch_target_pc")
 177         self.output_pc = Signal(32, name="fetch_output_pc")
 178         self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
 179         self.output_state = Signal(fetch_output_state,name="fetch_output_state")
 180
 181     def get_fetch_action(self, dc, load_store_misaligned, mi,
 182                          branch_taken, misaligned_jump_target,
 183                          csr_op_is_valid):
 184         c = {}
 185         c["default"] = self.action.eq(FA.default) # XXX should be 32'XXXXXXXX?
 186         c[FOS.empty] = self.action.eq(FA.default)
 187         c[FOS.trap] = self.action.eq(FA.ack_trap)
 188
 189         # illegal instruction -> error trap
 190         i= If((dc.act & DA.trap_illegal_instruction) != 0,
 191                  self.action.eq(FA.error_trap)
 192               )
 193
 194         # ecall / ebreak -> noerror trap
 195         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
 196                  self.action.eq(FA.noerror_trap))
 197
 198         # load/store: check alignment, check wait
 199         i = i.Elif((dc.act & (DA.load | DA.store)) != 0,
 200                 If((load_store_misaligned | ~mi.rw_address_valid),
 201                     self.action.eq(FA.error_trap) # misaligned or invalid addr
 202                 ).Elif(mi.rw_wait,
 203                     self.action.eq(FA.wait) # wait
 204                 ).Else(
 205                     self.action.eq(FA.default) # ok
 206                 )
 207               )
 208
 209         # fence
 210         i = i.Elif((dc.act & DA.fence) != 0,
 211                  self.action.eq(FA.fence))
 212
 213         # branch -> misaligned=error, otherwise jump
 214         i = i.Elif((dc.act & DA.branch) != 0,
 215                 If(misaligned_jump_target,
 216                     self.action.eq(FA.error_trap)
 217                 ).Else(
 218                     self.action.eq(FA.jump)
 219                 )
 220               )
 221
 222         # jal/jalr -> misaligned=error, otherwise jump
 223         i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
 224                 If(misaligned_jump_target,
 225                     self.action.eq(FA.error_trap)
 226                 ).Else(
 227                     self.action.eq(FA.jump)
 228                 )
 229               )
 230
 231         # csr -> opvalid=ok, else error trap
 232         i = i.Elif((dc.act & DA.csr) != 0,
 233                 If(csr_op_is_valid,
 234                     self.action.eq(FA.default)
 235                 ).Else(
 236                     self.action.eq(FA.error_trap)
 237                 )
 238               )
 239
 240         c[FOS.valid] = i
 241
 242         return Case(self.output_state, c)
 243
 244
 245 class CPU(Module):
 246     """
 247     """
 248
 249     def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
 250         """ returns whether a load/store is misaligned
 251         """
 252         return Case(funct3[:2],
 253                 { F3.sb: ls.eq(Constant(0)),
 254                   F3.sh: ls.eq(load_store_address_low_2[0] != 0),
 255                   F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
 256                   "default": ls.eq(Constant(1))
 257                 })
 258
 259     def get_lsbm(self, dc):
 260         return Cat(Constant(1),
 261                    Mux((dc.funct3[1] | dc.funct3[0]),
 262                        Constant(1), Constant(0)),
 263                    Mux((dc.funct3[1]),
 264                        Constant(0b11, 2), Constant(0, 2)))
 265
 266     # XXX this happens to get done by various self.sync actions
 267     #def reset_to_initial(self, m, mstatus, mie, registers):
 268     #    return [m.mcause.eq(0),
 269     #            ]
 270
 271     def write_register(self, register_number, value):
 272         return If(register_number != 0,
 273                   self.registers[register_number].eq(value)
 274                )
 275
 276     def evaluate_csr_funct3_op(self, funct3, previous_value, written_value):
 277         c = { "default": Constant(0, 32)}
 278         for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value
 279         for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value
 280         for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
 281         return Case(funct3, c)
 282
 283     """
 284     task handle_trap;
 285     begin
 286         mstatus_mpie = mstatus_mie;
 287         mstatus_mie = 0;
 288         mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
 289         if(fetch_action == `fetch_action_ack_trap) begin
 290             mcause = `cause_instruction_access_fault;
 291         end
 292         else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 293             mcause = `cause_illegal_instruction;
 294         end
 295         else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 296             mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
 297         end
 298         else if((decode_action & `decode_action_load) != 0) begin
 299             if(load_store_misaligned)
 300                 mcause = `cause_load_address_misaligned;
 301             else
 302                 mcause = `cause_load_access_fault;
 303         end
 304         else if((decode_action & `decode_action_store) != 0) begin
 305             if(load_store_misaligned)
 306                 mcause = `cause_store_amo_address_misaligned;
 307             else
 308                 mcause = `cause_store_amo_access_fault;
 309         end
 310         else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
 311             mcause = `cause_instruction_address_misaligned;
 312         end
 313         else begin
 314             mcause = `cause_illegal_instruction;
 315         end
 316     end
 317     endtask
 318     """
 319
 320     def __init__(self):
 321         self.clk = ClockSignal()
 322         self.reset = ResetSignal()
 323         self.tty_write = Signal()
 324         self.tty_write_data = Signal(8)
 325         self.tty_write_busy = Signal()
 326         self.switch_2 = Signal()
 327         self.switch_3 = Signal()
 328         self.led_1 = Signal()
 329         self.led_3 = Signal()
 330
 331         ram_size = Constant(0x8000)
 332         ram_start = Constant(0x10000, 32)
 333         reset_vector = Signal(32)
 334         mtvec = Signal(32)
 335
 336         reset_vector.eq(ram_start)
 337         mtvec.eq(ram_start + 0x40)
 338
 339         l = []
 340         for i in range(31):
 341             r = Signal(32, name="register%d" % i)
 342             l.append(r)
 343             self.sync += r.eq(Constant(0, 32))
 344         self.registers = Array(l)
 345
 346         mi = MemoryInterface()
 347
 348         mii = Instance("cpu_memory_interface", name="memory_instance",
 349                     p_ram_size = ram_size,
 350                     p_ram_start = ram_start,
 351                     i_clk=ClockSignal(),
 352                     i_rst=ResetSignal(),
 353                     i_fetch_address = mi.fetch_address,
 354                     o_fetch_data = mi.fetch_data,
 355                     o_fetch_valid = mi.fetch_valid,
 356                     i_rw_address = mi.rw_address,
 357                     i_rw_byte_mask = mi.rw_byte_mask,
 358                     i_rw_read_not_write = mi.rw_read_not_write,
 359                     i_rw_active = mi.rw_active,
 360                     i_rw_data_in = mi.rw_data_in,
 361                     o_rw_data_out = mi.rw_data_out,
 362                     o_rw_address_valid = mi.rw_address_valid,
 363                     o_rw_wait = mi.rw_wait,
 364                     o_tty_write = self.tty_write,
 365                     o_tty_write_data = self.tty_write_data,
 366                     i_tty_write_busy = self.tty_write_busy,
 367                     i_switch_2 = self.switch_2,
 368                     i_switch_3 = self.switch_3,
 369                     o_led_1 = self.led_1,
 370                     o_led_3 = self.led_3
 371                   )
 372         self.specials += mii
 373
 374         ft = Fetch(self.comb, self.sync)
 375
 376         fs = Instance("CPUFetchStage", name="fetch_stage",
 377             i_clk=ClockSignal(),
 378             i_rst=ResetSignal(),
 379             o_memory_interface_fetch_address = mi.fetch_address,
 380             i_memory_interface_fetch_data = mi.fetch_data,
 381             i_memory_interface_fetch_valid = mi.fetch_valid,
 382             i_fetch_action = ft.action,
 383             i_target_pc = ft.target_pc,
 384             o_output_pc = ft.output_pc,
 385             o_output_instruction = ft.output_instruction,
 386             o_output_state = ft.output_state,
 387             i_reset_vector = reset_vector,
 388             i_mtvec = mtvec,
 389         )
 390         self.specials += fs
 391
 392         dc = Decoder()
 393
 394         cd = Instance("CPUDecoder", name="decoder",
 395             i_instruction = ft.output_instruction,
 396             o_funct7 = dc.funct7,
 397             o_funct3 = dc.funct3,
 398             o_rd = dc.rd,
 399             o_rs1 = dc.rs1,
 400             o_rs2 = dc.rs2,
 401             o_immediate = dc.immediate,
 402             o_opcode = dc.opcode,
 403             o_decode_action = dc.act
 404         )
 405         self.specials += cd
 406
 407         register_rs1 = Signal(32)
 408         register_rs2 = Signal(32)
 409         self.comb += If(dc.rs1 == 0,
 410                         register_rs1.eq(0)
 411                      ).Else(
 412                         register_rs1.eq(self.registers[dc.rs1-1]))
 413         self.comb += If(dc.rs2 == 0,
 414                         register_rs2.eq(0)
 415                      ).Else(
 416                         register_rs2.eq(self.registers[dc.rs2-1]))
 417
 418         load_store_address = Signal(32)
 419         load_store_address_low_2 = Signal(2)
 420
 421         self.comb += load_store_address.eq(dc.immediate + register_rs1)
 422         self.comb += load_store_address_low_2.eq(
 423                             dc.immediate[:2] + register_rs1[:2])
 424
 425         load_store_misaligned = Signal()
 426
 427         lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3,
 428                                      load_store_address_low_2)
 429         self.comb += lsa
 430
 431         # XXX rwaddr not 31:2 any more
 432         self.comb += mi.rw_address.eq(load_store_address[2:])
 433
 434         unshifted_load_store_byte_mask = Signal(4)
 435
 436         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc))
 437
 438         # XXX yuck.  this will cause migen simulation to fail
 439         # (however conversion to verilog works)
 440         self.comb += mi.rw_byte_mask.eq(
 441                 _Operator("<<", [unshifted_load_store_byte_mask,
 442                                         load_store_address_low_2]))
 443
 444         # XXX not obvious
 445         b3 = Mux(load_store_address_low_2[1],
 446                  Mux(load_store_address_low_2[0], register_rs2[0:8],
 447                                                   register_rs2[8:16]),
 448                  Mux(load_store_address_low_2[0], register_rs2[16:24],
 449                                                   register_rs2[24:32]))
 450         b2 = Mux(load_store_address_low_2[1], register_rs2[0:8],
 451                                               register_rs2[16:24])
 452         b1 = Mux(load_store_address_low_2[0], register_rs2[0:8],
 453                                               register_rs2[8:16])
 454         b0 = register_rs2[0:8]
 455
 456         self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
 457
 458         # XXX not obvious
 459         unmasked_loaded_value = Signal(32)
 460
 461         b0 = Mux(load_store_address_low_2[1],
 462                  Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
 463                                                   mi.rw_data_out[16:24]),
 464                  Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
 465                                                   mi.rw_data_out[0:8]))
 466         b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
 467                                               mi.rw_data_out[8:16])
 468         b23 = mi.rw_data_out[16:32]
 469
 470         self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
 471
 472         # XXX not obvious
 473         loaded_value = Signal(32)
 474
 475         b0 = unmasked_loaded_value[0:8]
 476         b1 = Mux(dc.funct3[0:2] == 0,
 477                 Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8),
 478                 unmasked_loaded_value[8:16])
 479         b2 = Mux(dc.funct3[1] == 0,
 480                 Replicate(~dc.funct3[2] &
 481                            Mux(dc.funct3[0], unmasked_loaded_value[15],
 482                                                   unmasked_loaded_value[7]),
 483                           16),
 484                 unmasked_loaded_value[16:32])
 485
 486         self.comb += loaded_value.eq(Cat(b0, b1, b2))
 487
 488         self.comb += mi.rw_active.eq(~self.reset
 489                         & (ft.output_state == FOS.valid)
 490                         & ~load_store_misaligned
 491                         & ((dc.act & (DA.load | DA.store)) != 0))
 492
 493         self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
 494
 495         # alu
 496         alu_a = Signal(32)
 497         alu_b = Signal(32)
 498         alu_result = Signal(32)
 499
 500         self.comb += alu_a.eq(register_rs1)
 501         self.comb += alu_b.eq(Mux(dc.opcode[5],
 502                                   register_rs2,
 503                                   dc.immediate))
 504
 505         ali = Instance("cpu_alu", name="alu",
 506             i_funct7 = dc.funct7,
 507             i_funct3 = dc.funct3,
 508             i_opcode = dc.opcode,
 509             i_a = alu_a,
 510             i_b = alu_b,
 511             o_result = alu_result
 512         )
 513         self.specials += ali
 514
 515         lui_auipc_result = Signal(32)
 516         self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
 517                                              dc.immediate,
 518                                              dc.immediate + ft.output_pc))
 519
 520         self.comb += ft.target_pc.eq(Cat(0,
 521                     Mux(dc.opcode != OP.jalr,
 522                                 ft.output_pc[1:32],
 523                                 register_rs1[1:32] + dc.immediate[1:32])))
 524
 525         misaligned_jump_target = Signal()
 526         self.comb += misaligned_jump_target.eq(ft.target_pc[1])
 527
 528         branch_arg_a = Signal(32)
 529         branch_arg_b = Signal(32)
 530         self.comb += branch_arg_a.eq(Cat( register_rs1[0:31],
 531                                           register_rs1[31] ^ ~dc.funct3[1]))
 532         self.comb += branch_arg_b.eq(Cat( register_rs2[0:31],
 533                                           register_rs2[31] ^ ~dc.funct3[1]))
 534
 535         branch_taken = Signal()
 536         self.comb += branch_taken.eq(dc.funct3[0] ^
 537                                      Mux(dc.funct3[2],
 538                                          branch_arg_a < branch_arg_b,
 539                                          branch_arg_a == branch_arg_b))
 540
 541         m = M(self.comb, self.sync)
 542         mstatus = MStatus(self.comb, self.sync)
 543         mie = MIE(self.comb, self.sync)
 544
 545         misa = Misa(self.comb, self.sync)
 546
 547         mvendorid = Signal(32)
 548         marchid = Signal(32)
 549         mimpid = Signal(32)
 550         mhartid = Signal(32)
 551         self.comb += mvendorid.eq(Constant(0, 32))
 552         self.comb += marchid.eq(Constant(0, 32))
 553         self.comb += mimpid.eq(Constant(0, 32))
 554         self.comb += mhartid.eq(Constant(0, 32))
 555
 556         mip = MIP(self.comb, self.sync)
 557
 558         csr_op_is_valid = Signal()
 559
 560         self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi,
 561                                  branch_taken, misaligned_jump_target,
 562                                  csr_op_is_valid)
 563 if __name__ == "__main__":
 564     example = CPU()
 565     print(verilog.convert(example,
 566          {
 567            example.tty_write,
 568            example.tty_write_data,
 569            example.tty_write_busy,
 570            example.switch_2,
 571            example.switch_3,
 572            example.led_1,
 573            example.led_3,
 574            }))
 575
 576 """
 577
 578     task handle_trap;
 579     begin
 580         mstatus_mpie = mstatus_mie;
 581         mstatus_mie = 0;
 582         mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
 583         if(fetch_action == `fetch_action_ack_trap) begin
 584             mcause = `cause_instruction_access_fault;
 585         end
 586         else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 587             mcause = `cause_illegal_instruction;
 588         end
 589         else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 590             mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
 591         end
 592         else if((decode_action & `decode_action_load) != 0) begin
 593             if(load_store_misaligned)
 594                 mcause = `cause_load_address_misaligned;
 595             else
 596                 mcause = `cause_load_access_fault;
 597         end
 598         else if((decode_action & `decode_action_store) != 0) begin
 599             if(load_store_misaligned)
 600                 mcause = `cause_store_amo_address_misaligned;
 601             else
 602                 mcause = `cause_store_amo_access_fault;
 603         end
 604         else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
 605             mcause = `cause_instruction_address_misaligned;
 606         end
 607         else begin
 608             mcause = `cause_illegal_instruction;
 609         end
 610     end
 611     endtask
 612
 613     wire [11:0] csr_number = decoder_immediate;
 614     wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
 615     wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
 616     wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
 617
 618     function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
 619     begin
 620         case(csr_number)
 621         `csr_ustatus,
 622         `csr_fflags,
 623         `csr_frm,
 624         `csr_fcsr,
 625         `csr_uie,
 626         `csr_utvec,
 627         `csr_uscratch,
 628         `csr_uepc,
 629         `csr_ucause,
 630         `csr_utval,
 631         `csr_uip,
 632         `csr_sstatus,
 633         `csr_sedeleg,
 634         `csr_sideleg,
 635         `csr_sie,
 636         `csr_stvec,
 637         `csr_scounteren,
 638         `csr_sscratch,
 639         `csr_sepc,
 640         `csr_scause,
 641         `csr_stval,
 642         `csr_sip,
 643         `csr_satp,
 644         `csr_medeleg,
 645         `csr_mideleg,
 646         `csr_dcsr,
 647         `csr_dpc,
 648         `csr_dscratch:
 649             get_csr_op_is_valid = 0;
 650         `csr_cycle,
 651         `csr_time,
 652         `csr_instret,
 653         `csr_cycleh,
 654         `csr_timeh,
 655         `csr_instreth,
 656         `csr_mvendorid,
 657         `csr_marchid,
 658         `csr_mimpid,
 659         `csr_mhartid:
 660             get_csr_op_is_valid = ~csr_writes;
 661         `csr_misa,
 662         `csr_mstatus,
 663         `csr_mie,
 664         `csr_mtvec,
 665         `csr_mscratch,
 666         `csr_mepc,
 667         `csr_mcause,
 668         `csr_mip:
 669             get_csr_op_is_valid = 1;
 670         `csr_mcounteren,
 671         `csr_mtval,
 672         `csr_mcycle,
 673         `csr_minstret,
 674         `csr_mcycleh,
 675         `csr_minstreth:
 676             // TODO: CSRs not implemented yet
 677             get_csr_op_is_valid = 0;
 678         endcase
 679     end
 680     endfunction
 681
 682     assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
 683
 684     wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
 685     wire [63:0] time_counter = 0; // TODO: implement time_counter
 686     wire [63:0] instret_counter = 0; // TODO: implement instret_counter
 687
 688     always @(posedge clk) begin:main_block
 689         if(reset) begin
 690             reset_to_initial();
 691             disable main_block;
 692         end
 693         case(fetch_output_state)
 694         `fetch_output_state_empty: begin
 695         end
 696         `fetch_output_state_trap: begin
 697             handle_trap();
 698         end
 699         `fetch_output_state_valid: begin:valid
 700             if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
 701                 handle_trap();
 702             end
 703             else if((decode_action & `decode_action_load) != 0) begin
 704                 if(~memory_interface_rw_wait)
 705                     write_register(decoder_rd, loaded_value);
 706             end
 707             else if((decode_action & `decode_action_op_op_imm) != 0) begin
 708                 write_register(decoder_rd, alu_result);
 709             end
 710             else if((decode_action & `decode_action_lui_auipc) != 0) begin
 711                 write_register(decoder_rd, lui_auipc_result);
 712             end
 713             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 714                 write_register(decoder_rd, fetch_output_pc + 4);
 715             end
 716             else if((decode_action & `decode_action_csr) != 0) begin:csr
 717                 reg [31:0] csr_output_value;
 718                 reg [31:0] csr_written_value;
 719                 csr_output_value = 32'hXXXXXXXX;
 720                 csr_written_value = 32'hXXXXXXXX;
 721                 case(csr_number)
 722                 `csr_cycle: begin
 723                     csr_output_value = cycle_counter[31:0];
 724                 end
 725                 `csr_time: begin
 726                     csr_output_value = time_counter[31:0];
 727                 end
 728                 `csr_instret: begin
 729                     csr_output_value = instret_counter[31:0];
 730                 end
 731                 `csr_cycleh: begin
 732                     csr_output_value = cycle_counter[63:32];
 733                 end
 734                 `csr_timeh: begin
 735                     csr_output_value = time_counter[63:32];
 736                 end
 737                 `csr_instreth: begin
 738                     csr_output_value = instret_counter[63:32];
 739                 end
 740                 `csr_mvendorid: begin
 741                     csr_output_value = mvendorid;
 742                 end
 743                 `csr_marchid: begin
 744                     csr_output_value = marchid;
 745                 end
 746                 `csr_mimpid: begin
 747                     csr_output_value = mimpid;
 748                 end
 749                 `csr_mhartid: begin
 750                     csr_output_value = mhartid;
 751                 end
 752                 `csr_misa: begin
 753                     csr_output_value = misa;
 754                 end
 755                 `csr_mstatus: begin
 756                     csr_output_value = make_mstatus(mstatus_tsr,
 757                                                     mstatus_tw,
 758                                                     mstatus_tvm,
 759                                                     mstatus_mxr,
 760                                                     mstatus_sum,
 761                                                     mstatus_mprv,
 762                                                     mstatus_xs,
 763                                                     mstatus_fs,
 764                                                     mstatus_mpp,
 765                                                     mstatus_spp,
 766                                                     mstatus_mpie,
 767                                                     mstatus_spie,
 768                                                     mstatus_upie,
 769                                                     mstatus_mie,
 770                                                     mstatus_sie,
 771                                                     mstatus_uie);
 772                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 773                     if(csr_writes) begin
 774                         mstatus_mpie = csr_written_value[7];
 775                         mstatus_mie = csr_written_value[3];
 776                     end
 777                 end
 778                 `csr_mie: begin
 779                     csr_output_value = 0;
 780                     csr_output_value[11] = mie_meie;
 781                     csr_output_value[9] = mie_seie;
 782                     csr_output_value[8] = mie_ueie;
 783                     csr_output_value[7] = mie_mtie;
 784                     csr_output_value[5] = mie_stie;
 785                     csr_output_value[4] = mie_utie;
 786                     csr_output_value[3] = mie_msie;
 787                     csr_output_value[1] = mie_ssie;
 788                     csr_output_value[0] = mie_usie;
 789                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 790                     if(csr_writes) begin
 791                         mie_meie = csr_written_value[11];
 792                         mie_mtie = csr_written_value[7];
 793                         mie_msie = csr_written_value[3];
 794                     end
 795                 end
 796                 `csr_mtvec: begin
 797                     csr_output_value = mtvec;
 798                 end
 799                 `csr_mscratch: begin
 800                     csr_output_value = mscratch;
 801                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 802                     if(csr_writes)
 803                         mscratch = csr_written_value;
 804                 end
 805                 `csr_mepc: begin
 806                     csr_output_value = mepc;
 807                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 808                     if(csr_writes)
 809                         mepc = csr_written_value;
 810                 end
 811                 `csr_mcause: begin
 812                     csr_output_value = mcause;
 813                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 814                     if(csr_writes)
 815                         mcause = csr_written_value;
 816                 end
 817                 `csr_mip: begin
 818                     csr_output_value = 0;
 819                     csr_output_value[11] = mip_meip;
 820                     csr_output_value[9] = mip_seip;
 821                     csr_output_value[8] = mip_ueip;
 822                     csr_output_value[7] = mip_mtip;
 823                     csr_output_value[5] = mip_stip;
 824                     csr_output_value[4] = mip_utip;
 825                     csr_output_value[3] = mip_msip;
 826                     csr_output_value[1] = mip_ssip;
 827                     csr_output_value[0] = mip_usip;
 828                 end
 829                 endcase
 830                 if(csr_reads)
 831                     write_register(decoder_rd, csr_output_value);
 832             end
 833             else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
 834                 // do nothing
 835             end
 836         end
 837         endcase
 838     end
 839
 840 endmodule
 841 """
 842