cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 from migen import *
  30 from migen.fhdl import verilog
  31 from migen.fhdl.structure import _Operator
  32
  33 from riscvdefs import *
  34 from cpudefs import *
  35
  36 class MemoryInterface:
  37     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  38     fetch_data = Signal(32, name="memory_interface_fetch_data")
  39     fetch_valid = Signal(name="memory_interface_fetch_valid")
  40     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  41     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  42     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  43     rw_active = Signal(name="memory_interface_rw_active")
  44     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  45     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  46     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  47     rw_wait = Signal(name="memory_interface_rw_wait")
  48
  49
  50 class CPU(Module):
  51     """
  52     """
  53
  54     def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
  55         return Case(funct3[:2],
  56                 { F3.sb: ls.eq(Constant(0)),
  57                   F3.sh: ls.eq(load_store_address_low_2[0] != 0),
  58                   F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
  59                   "default": ls.eq(Constant(1))
  60                 })
  61
  62     def get_lsbm(self, decoder_funct3):
  63         return Cat(Constant(1),
  64                    Mux((decoder_funct3[1] | decoder_funct3[0]),
  65                        Constant(1), Constant(0)),
  66                    Mux((decoder_funct3[1]),
  67                        Constant(0b11, 2), Constant(0, 2)))
  68
  69     def __init__(self):
  70         #self.clk = ClockSignal()
  71         #self.reset = ResetSignal()
  72         self.tty_write = Signal()
  73         self.tty_write_data = Signal(8)
  74         self.tty_write_busy = Signal()
  75         self.switch_2 = Signal()
  76         self.switch_3 = Signal()
  77         self.led_1 = Signal()
  78         self.led_3 = Signal()
  79
  80         ram_size = Constant(0x8000)
  81         ram_start = Constant(0x10000, 32)
  82         reset_vector = Signal(32)
  83         mtvec = Signal(32)
  84
  85         reset_vector.eq(ram_start)
  86         mtvec.eq(ram_start + 0x40)
  87
  88         l = []
  89         for i in range(31):
  90             l.append(Signal(32, name="register%d" % i))
  91         registers = Array(l)
  92
  93         mi = MemoryInterface()
  94
  95         mii = Instance("cpu_memory_interface", name="memory_instance",
  96                     p_ram_size = ram_size,
  97                     p_ram_start = ram_start,
  98                     i_clk=ClockSignal(),
  99                     i_rst=ResetSignal(),
 100                     i_fetch_address = mi.fetch_address,
 101                     o_fetch_data = mi.fetch_data,
 102                     o_fetch_valid = mi.fetch_valid,
 103                     i_rw_address = mi.rw_address,
 104                     i_rw_byte_mask = mi.rw_byte_mask,
 105                     i_rw_read_not_write = mi.rw_read_not_write,
 106                     i_rw_active = mi.rw_active,
 107                     i_rw_data_in = mi.rw_data_in,
 108                     o_rw_data_out = mi.rw_data_out,
 109                     o_rw_address_valid = mi.rw_address_valid,
 110                     o_rw_wait = mi.rw_wait,
 111                     o_tty_write = self.tty_write,
 112                     o_tty_write_data = self.tty_write_data,
 113                     i_tty_write_busy = self.tty_write_busy,
 114                     i_switch_2 = self.switch_2,
 115                     i_switch_3 = self.switch_3,
 116                     o_led_1 = self.led_1,
 117                     o_led_3 = self.led_3
 118                   )
 119         self.specials += mii
 120
 121         fetch_act = Signal(fetch_action)
 122         fetch_target_pc = Signal(32)
 123         fetch_output_pc = Signal(32)
 124         fetch_output_instruction = Signal(32)
 125         fetch_output_st = Signal(fetch_output_state)
 126
 127         fs = Instance("CPUFetchStage", name="fetch_stage",
 128             i_clk=ClockSignal(),
 129             i_rst=ResetSignal(),
 130             o_memory_interface_fetch_address = mi.fetch_address,
 131             i_memory_interface_fetch_data = mi.fetch_data,
 132             i_memory_interface_fetch_valid = mi.fetch_valid,
 133             i_fetch_action = fetch_act,
 134             i_target_pc = fetch_target_pc,
 135             o_output_pc = fetch_output_pc,
 136             o_output_instruction = fetch_output_instruction,
 137             o_output_state = fetch_output_st,
 138             i_reset_vector = reset_vector,
 139             i_mtvec = mtvec,
 140         )
 141         self.specials += fs
 142
 143         decoder_funct7 = Signal(7)
 144         decoder_funct3 = Signal(3)
 145         decoder_rd = Signal(5)
 146         decoder_rs1 = Signal(5)
 147         decoder_rs2 = Signal(5)
 148         decoder_immediate = Signal(32)
 149         decoder_opcode = Signal(7)
 150         decode_act = Signal(decode_action)
 151
 152         cd = Instance("CPUDecoder", name="decoder",
 153             i_instruction = fetch_output_instruction,
 154             o_funct7 = decoder_funct7,
 155             o_funct3 = decoder_funct3,
 156             o_rd = decoder_rd,
 157             o_rs1 = decoder_rs1,
 158             o_rs2 = decoder_rs2,
 159             o_immediate = decoder_immediate,
 160             o_opcode = decoder_opcode,
 161             o_decode_action = decode_act
 162         )
 163         self.specials += cd
 164
 165         register_rs1 = Signal(32)
 166         register_rs2 = Signal(32)
 167         self.comb += If(decoder_rs1 == 0,
 168                         register_rs1.eq(0)
 169                      ).Else(
 170                         register_rs1.eq(registers[decoder_rs1-1]))
 171         self.comb += If(decoder_rs2 == 0,
 172                         register_rs2.eq(0)
 173                      ).Else(
 174                         register_rs2.eq(registers[decoder_rs2-1]))
 175
 176         load_store_address = Signal(32)
 177         load_store_address_low_2 = Signal(2)
 178
 179         self.comb += load_store_address.eq(decoder_immediate + register_rs1)
 180         self.comb += load_store_address_low_2.eq(
 181                             decoder_immediate[:2] + register_rs1[:2])
 182
 183         load_store_misaligned = Signal()
 184
 185         lsa = self.get_ls_misaligned(load_store_misaligned, decoder_funct3,
 186                                      load_store_address_low_2)
 187         self.comb += lsa
 188
 189         # XXX rwaddr not 31:2 any more
 190         self.comb += mi.rw_address.eq(load_store_address[2:])
 191
 192         unshifted_load_store_byte_mask = Signal(4)
 193
 194         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(
 195                                                        decoder_funct3))
 196
 197         # XXX yuck.  this will cause migen simulation to fail
 198         # (however conversion to verilog works)
 199         self.comb += mi.rw_byte_mask.eq(
 200                 _Operator("<<", [unshifted_load_store_byte_mask,
 201                                         load_store_address_low_2]))
 202
 203 if __name__ == "__main__":
 204     example = CPU()
 205     print(verilog.convert(example,
 206          {
 207            example.tty_write,
 208            example.tty_write_data,
 209            example.tty_write_busy,
 210            example.switch_2,
 211            example.switch_3,
 212            example.led_1,
 213            example.led_3,
 214            }))
 215
 216 """
 217
 218     assign memory_interface_rw_byte_mask = unshifted_load_store_byte_mask << load_store_address_low_2;
 219
 220     assign memory_interface_rw_data_in[31:24] = load_store_address_low_2[1]
 221                                                 ? (load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8])
 222                                                 : (load_store_address_low_2[0] ? register_rs2[23:16] : register_rs2[31:24]);
 223     assign memory_interface_rw_data_in[23:16] = load_store_address_low_2[1] ? register_rs2[7:0] : register_rs2[23:16];
 224     assign memory_interface_rw_data_in[15:8] = load_store_address_low_2[0] ? register_rs2[7:0] : register_rs2[15:8];
 225     assign memory_interface_rw_data_in[7:0] = register_rs2[7:0];
 226
 227     wire [31:0] unmasked_loaded_value;
 228
 229     assign unmasked_loaded_value[7:0] = load_store_address_low_2[1]
 230                                         ? (load_store_address_low_2[0] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[23:16])
 231                                         : (load_store_address_low_2[0] ? memory_interface_rw_data_out[15:8] : memory_interface_rw_data_out[7:0]);
 232     assign unmasked_loaded_value[15:8] = load_store_address_low_2[1] ? memory_interface_rw_data_out[31:24] : memory_interface_rw_data_out[15:8];
 233     assign unmasked_loaded_value[31:16] = memory_interface_rw_data_out[31:16];
 234
 235     wire [31:0] loaded_value;
 236
 237     assign loaded_value[7:0] = unmasked_loaded_value[7:0];
 238     assign loaded_value[15:8] = decoder_funct3[1:0] == 0 ? ({8{~decoder_funct3[2] & unmasked_loaded_value[7]}}) : unmasked_loaded_value[15:8];
 239     assign loaded_value[31:16] = decoder_funct3[1] == 0 ? ({16{~decoder_funct3[2] & (decoder_funct3[0] ? unmasked_loaded_value[15] : unmasked_loaded_value[7])}}) : unmasked_loaded_value[31:16];
 240
 241     assign memory_interface_rw_active = ~reset
 242                                         & (fetch_output_state == `fetch_output_state_valid)
 243                                         & ~load_store_misaligned
 244                                         & ((decode_action & (`decode_action_load | `decode_action_store)) != 0);
 245
 246     assign memory_interface_rw_read_not_write = ~decoder_opcode[5];
 247
 248     wire [31:0] alu_a = register_rs1;
 249     wire [31:0] alu_b = decoder_opcode[5] ? register_rs2 : decoder_immediate;
 250     wire [31:0] alu_result;
 251
 252     cpu_alu alu(
 253         .funct7(decoder_funct7),
 254         .funct3(decoder_funct3),
 255         .opcode(decoder_opcode),
 256         .a(alu_a),
 257         .b(alu_b),
 258         .result(alu_result)
 259         );
 260
 261     wire [31:0] lui_auipc_result = decoder_opcode[5] ? decoder_immediate : decoder_immediate + fetch_output_pc;
 262
 263     assign fetch_target_pc[31:1] = ((decoder_opcode != `opcode_jalr ? fetch_output_pc[31:1] : register_rs1[31:1]) + decoder_immediate[31:1]);
 264     assign fetch_target_pc[0] = 0;
 265
 266     wire misaligned_jump_target = fetch_target_pc[1];
 267
 268     wire [31:0] branch_arg_a = {register_rs1[31] ^ ~decoder_funct3[1], register_rs1[30:0]};
 269     wire [31:0] branch_arg_b = {register_rs2[31] ^ ~decoder_funct3[1], register_rs2[30:0]};
 270
 271     wire branch_taken = decoder_funct3[0] ^ (decoder_funct3[2] ? branch_arg_a < branch_arg_b : branch_arg_a == branch_arg_b);
 272
 273     reg [31:0] mcause = 0;
 274     reg [31:0] mepc = 32'hXXXXXXXX;
 275     reg [31:0] mscratch = 32'hXXXXXXXX;
 276
 277     reg mstatus_mpie = 1'bX;
 278     reg mstatus_mie = 0;
 279     parameter mstatus_mprv = 0;
 280     parameter mstatus_tsr = 0;
 281     parameter mstatus_tw = 0;
 282     parameter mstatus_tvm = 0;
 283     parameter mstatus_mxr = 0;
 284     parameter mstatus_sum = 0;
 285     parameter mstatus_xs = 0;
 286     parameter mstatus_fs = 0;
 287     parameter mstatus_mpp = 2'b11;
 288     parameter mstatus_spp = 0;
 289     parameter mstatus_spie = 0;
 290     parameter mstatus_upie = 0;
 291     parameter mstatus_sie = 0;
 292     parameter mstatus_uie = 0;
 293
 294     reg mie_meie = 1'bX;
 295     reg mie_mtie = 1'bX;
 296     reg mie_msie = 1'bX;
 297     parameter mie_seie = 0;
 298     parameter mie_ueie = 0;
 299     parameter mie_stie = 0;
 300     parameter mie_utie = 0;
 301     parameter mie_ssie = 0;
 302     parameter mie_usie = 0;
 303
 304     task reset_to_initial;
 305     begin
 306         mcause = 0;
 307         mepc = 32'hXXXXXXXX;
 308         mscratch = 32'hXXXXXXXX;
 309         mstatus_mie = 0;
 310         mstatus_mpie = 1'bX;
 311         mie_meie = 1'bX;
 312         mie_mtie = 1'bX;
 313         mie_msie = 1'bX;
 314         registers['h01] <= 32'hXXXXXXXX;
 315         registers['h02] <= 32'hXXXXXXXX;
 316         registers['h03] <= 32'hXXXXXXXX;
 317         registers['h04] <= 32'hXXXXXXXX;
 318         registers['h05] <= 32'hXXXXXXXX;
 319         registers['h06] <= 32'hXXXXXXXX;
 320         registers['h07] <= 32'hXXXXXXXX;
 321         registers['h08] <= 32'hXXXXXXXX;
 322         registers['h09] <= 32'hXXXXXXXX;
 323         registers['h0A] <= 32'hXXXXXXXX;
 324         registers['h0B] <= 32'hXXXXXXXX;
 325         registers['h0C] <= 32'hXXXXXXXX;
 326         registers['h0D] <= 32'hXXXXXXXX;
 327         registers['h0E] <= 32'hXXXXXXXX;
 328         registers['h0F] <= 32'hXXXXXXXX;
 329         registers['h10] <= 32'hXXXXXXXX;
 330         registers['h11] <= 32'hXXXXXXXX;
 331         registers['h12] <= 32'hXXXXXXXX;
 332         registers['h13] <= 32'hXXXXXXXX;
 333         registers['h14] <= 32'hXXXXXXXX;
 334         registers['h15] <= 32'hXXXXXXXX;
 335         registers['h16] <= 32'hXXXXXXXX;
 336         registers['h17] <= 32'hXXXXXXXX;
 337         registers['h18] <= 32'hXXXXXXXX;
 338         registers['h19] <= 32'hXXXXXXXX;
 339         registers['h1A] <= 32'hXXXXXXXX;
 340         registers['h1B] <= 32'hXXXXXXXX;
 341         registers['h1C] <= 32'hXXXXXXXX;
 342         registers['h1D] <= 32'hXXXXXXXX;
 343         registers['h1E] <= 32'hXXXXXXXX;
 344         registers['h1F] <= 32'hXXXXXXXX;
 345     end
 346     endtask
 347
 348     task write_register(input [4:0] register_number, input [31:0] value);
 349     begin
 350         if(register_number != 0)
 351             registers[register_number] <= value;
 352     end
 353     endtask
 354
 355     function [31:0] evaluate_csr_funct3_operation(input [2:0] funct3, input [31:0] previous_value, input [31:0] written_value);
 356     begin
 357         case(funct3)
 358         `funct3_csrrw, `funct3_csrrwi:
 359             evaluate_csr_funct3_operation = written_value;
 360         `funct3_csrrs, `funct3_csrrsi:
 361             evaluate_csr_funct3_operation = written_value | previous_value;
 362         `funct3_csrrc, `funct3_csrrci:
 363             evaluate_csr_funct3_operation = ~written_value & previous_value;
 364         default:
 365             evaluate_csr_funct3_operation = 32'hXXXXXXXX;
 366         endcase
 367     end
 368     endfunction
 369
 370     parameter misa_a = 1'b0;
 371     parameter misa_b = 1'b0;
 372     parameter misa_c = 1'b0;
 373     parameter misa_d = 1'b0;
 374     parameter misa_e = 1'b0;
 375     parameter misa_f = 1'b0;
 376     parameter misa_g = 1'b0;
 377     parameter misa_h = 1'b0;
 378     parameter misa_i = 1'b1;
 379     parameter misa_j = 1'b0;
 380     parameter misa_k = 1'b0;
 381     parameter misa_l = 1'b0;
 382     parameter misa_m = 1'b0;
 383     parameter misa_n = 1'b0;
 384     parameter misa_o = 1'b0;
 385     parameter misa_p = 1'b0;
 386     parameter misa_q = 1'b0;
 387     parameter misa_r = 1'b0;
 388     parameter misa_s = 1'b0;
 389     parameter misa_t = 1'b0;
 390     parameter misa_u = 1'b0;
 391     parameter misa_v = 1'b0;
 392     parameter misa_w = 1'b0;
 393     parameter misa_x = 1'b0;
 394     parameter misa_y = 1'b0;
 395     parameter misa_z = 1'b0;
 396     parameter misa = {
 397         2'b01,
 398         4'b0,
 399         misa_z,
 400         misa_y,
 401         misa_x,
 402         misa_w,
 403         misa_v,
 404         misa_u,
 405         misa_t,
 406         misa_s,
 407         misa_r,
 408         misa_q,
 409         misa_p,
 410         misa_o,
 411         misa_n,
 412         misa_m,
 413         misa_l,
 414         misa_k,
 415         misa_j,
 416         misa_i,
 417         misa_h,
 418         misa_g,
 419         misa_f,
 420         misa_e,
 421         misa_d,
 422         misa_c,
 423         misa_b,
 424         misa_a};
 425
 426     parameter mvendorid = 32'b0;
 427     parameter marchid = 32'b0;
 428     parameter mimpid = 32'b0;
 429     parameter mhartid = 32'b0;
 430
 431     function [31:0] make_mstatus(input mstatus_tsr,
 432         input mstatus_tw,
 433         input mstatus_tvm,
 434         input mstatus_mxr,
 435         input mstatus_sum,
 436         input mstatus_mprv,
 437         input [1:0] mstatus_xs,
 438         input [1:0] mstatus_fs,
 439         input [1:0] mstatus_mpp,
 440         input mstatus_spp,
 441         input mstatus_mpie,
 442         input mstatus_spie,
 443         input mstatus_upie,
 444         input mstatus_mie,
 445         input mstatus_sie,
 446         input mstatus_uie);
 447     begin
 448         make_mstatus = {(mstatus_xs == 2'b11) | (mstatus_fs == 2'b11),
 449             8'b0,
 450             mstatus_tsr,
 451             mstatus_tw,
 452             mstatus_tvm,
 453             mstatus_mxr,
 454             mstatus_sum,
 455             mstatus_mprv,
 456             mstatus_xs,
 457             mstatus_fs,
 458             mstatus_mpp,
 459             2'b0,
 460             mstatus_spp,
 461             mstatus_mpie,
 462             1'b0,
 463             mstatus_spie,
 464             mstatus_upie,
 465             mstatus_mie,
 466             1'b0,
 467             mstatus_sie,
 468             mstatus_uie};
 469     end
 470     endfunction
 471
 472     wire mip_meip = 0; // TODO: implement external interrupts
 473     parameter mip_seip = 0;
 474     parameter mip_ueip = 0;
 475     wire mip_mtip = 0; // TODO: implement timer interrupts
 476     parameter mip_stip = 0;
 477     parameter mip_utip = 0;
 478     parameter mip_msip = 0;
 479     parameter mip_ssip = 0;
 480     parameter mip_usip = 0;
 481
 482     wire csr_op_is_valid;
 483
 484     function `fetch_action get_fetch_action(
 485         input `fetch_output_state fetch_output_state,
 486         input `decode_action decode_action,
 487         input load_store_misaligned,
 488         input memory_interface_rw_address_valid,
 489         input memory_interface_rw_wait,
 490         input branch_taken,
 491         input misaligned_jump_target,
 492         input csr_op_is_valid
 493         );
 494     begin
 495         case(fetch_output_state)
 496         `fetch_output_state_empty:
 497             get_fetch_action = `fetch_action_default;
 498         `fetch_output_state_trap:
 499             get_fetch_action = `fetch_action_ack_trap;
 500         `fetch_output_state_valid: begin
 501             if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 502                 get_fetch_action = `fetch_action_error_trap;
 503             end
 504             else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 505                 get_fetch_action = `fetch_action_noerror_trap;
 506             end
 507             else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
 508                 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
 509                     get_fetch_action = `fetch_action_error_trap;
 510                 end
 511                 else if(memory_interface_rw_wait) begin
 512                     get_fetch_action = `fetch_action_wait;
 513                 end
 514                 else begin
 515                     get_fetch_action = `fetch_action_default;
 516                 end
 517             end
 518             else if((decode_action & `decode_action_fence_i) != 0) begin
 519                 get_fetch_action = `fetch_action_fence;
 520             end
 521             else if((decode_action & `decode_action_branch) != 0) begin
 522                 if(branch_taken) begin
 523                     if(misaligned_jump_target) begin
 524                         get_fetch_action = `fetch_action_error_trap;
 525                     end
 526                     else begin
 527                         get_fetch_action = `fetch_action_jump;
 528                     end
 529                 end
 530                 else
 531                 begin
 532                     get_fetch_action = `fetch_action_default;
 533                 end
 534             end
 535             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 536                 if(misaligned_jump_target) begin
 537                     get_fetch_action = `fetch_action_error_trap;
 538                 end
 539                 else begin
 540                     get_fetch_action = `fetch_action_jump;
 541                 end
 542             end
 543             else if((decode_action & `decode_action_csr) != 0) begin
 544                 if(csr_op_is_valid)
 545                     get_fetch_action = `fetch_action_default;
 546                 else
 547                     get_fetch_action = `fetch_action_error_trap;
 548             end
 549             else begin
 550                 get_fetch_action = `fetch_action_default;
 551             end
 552         end
 553         default:
 554             get_fetch_action = 32'hXXXXXXXX;
 555         endcase
 556     end
 557     endfunction
 558
 559     assign fetch_action = get_fetch_action(
 560         fetch_output_state,
 561         decode_action,
 562         load_store_misaligned,
 563         memory_interface_rw_address_valid,
 564         memory_interface_rw_wait,
 565         branch_taken,
 566         misaligned_jump_target,
 567         csr_op_is_valid
 568         );
 569
 570     task handle_trap;
 571     begin
 572         mstatus_mpie = mstatus_mie;
 573         mstatus_mie = 0;
 574         mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
 575         if(fetch_action == `fetch_action_ack_trap) begin
 576             mcause = `cause_instruction_access_fault;
 577         end
 578         else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 579             mcause = `cause_illegal_instruction;
 580         end
 581         else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 582             mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
 583         end
 584         else if((decode_action & `decode_action_load) != 0) begin
 585             if(load_store_misaligned)
 586                 mcause = `cause_load_address_misaligned;
 587             else
 588                 mcause = `cause_load_access_fault;
 589         end
 590         else if((decode_action & `decode_action_store) != 0) begin
 591             if(load_store_misaligned)
 592                 mcause = `cause_store_amo_address_misaligned;
 593             else
 594                 mcause = `cause_store_amo_access_fault;
 595         end
 596         else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
 597             mcause = `cause_instruction_address_misaligned;
 598         end
 599         else begin
 600             mcause = `cause_illegal_instruction;
 601         end
 602     end
 603     endtask
 604
 605     wire [11:0] csr_number = decoder_immediate;
 606     wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
 607     wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
 608     wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
 609
 610     function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
 611     begin
 612         case(csr_number)
 613         `csr_ustatus,
 614         `csr_fflags,
 615         `csr_frm,
 616         `csr_fcsr,
 617         `csr_uie,
 618         `csr_utvec,
 619         `csr_uscratch,
 620         `csr_uepc,
 621         `csr_ucause,
 622         `csr_utval,
 623         `csr_uip,
 624         `csr_sstatus,
 625         `csr_sedeleg,
 626         `csr_sideleg,
 627         `csr_sie,
 628         `csr_stvec,
 629         `csr_scounteren,
 630         `csr_sscratch,
 631         `csr_sepc,
 632         `csr_scause,
 633         `csr_stval,
 634         `csr_sip,
 635         `csr_satp,
 636         `csr_medeleg,
 637         `csr_mideleg,
 638         `csr_dcsr,
 639         `csr_dpc,
 640         `csr_dscratch:
 641             get_csr_op_is_valid = 0;
 642         `csr_cycle,
 643         `csr_time,
 644         `csr_instret,
 645         `csr_cycleh,
 646         `csr_timeh,
 647         `csr_instreth,
 648         `csr_mvendorid,
 649         `csr_marchid,
 650         `csr_mimpid,
 651         `csr_mhartid:
 652             get_csr_op_is_valid = ~csr_writes;
 653         `csr_misa,
 654         `csr_mstatus,
 655         `csr_mie,
 656         `csr_mtvec,
 657         `csr_mscratch,
 658         `csr_mepc,
 659         `csr_mcause,
 660         `csr_mip:
 661             get_csr_op_is_valid = 1;
 662         `csr_mcounteren,
 663         `csr_mtval,
 664         `csr_mcycle,
 665         `csr_minstret,
 666         `csr_mcycleh,
 667         `csr_minstreth:
 668             // TODO: CSRs not implemented yet
 669             get_csr_op_is_valid = 0;
 670         endcase
 671     end
 672     endfunction
 673
 674     assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
 675
 676     wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
 677     wire [63:0] time_counter = 0; // TODO: implement time_counter
 678     wire [63:0] instret_counter = 0; // TODO: implement instret_counter
 679
 680     always @(posedge clk) begin:main_block
 681         if(reset) begin
 682             reset_to_initial();
 683             disable main_block;
 684         end
 685         case(fetch_output_state)
 686         `fetch_output_state_empty: begin
 687         end
 688         `fetch_output_state_trap: begin
 689             handle_trap();
 690         end
 691         `fetch_output_state_valid: begin:valid
 692             if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
 693                 handle_trap();
 694             end
 695             else if((decode_action & `decode_action_load) != 0) begin
 696                 if(~memory_interface_rw_wait)
 697                     write_register(decoder_rd, loaded_value);
 698             end
 699             else if((decode_action & `decode_action_op_op_imm) != 0) begin
 700                 write_register(decoder_rd, alu_result);
 701             end
 702             else if((decode_action & `decode_action_lui_auipc) != 0) begin
 703                 write_register(decoder_rd, lui_auipc_result);
 704             end
 705             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 706                 write_register(decoder_rd, fetch_output_pc + 4);
 707             end
 708             else if((decode_action & `decode_action_csr) != 0) begin:csr
 709                 reg [31:0] csr_output_value;
 710                 reg [31:0] csr_written_value;
 711                 csr_output_value = 32'hXXXXXXXX;
 712                 csr_written_value = 32'hXXXXXXXX;
 713                 case(csr_number)
 714                 `csr_cycle: begin
 715                     csr_output_value = cycle_counter[31:0];
 716                 end
 717                 `csr_time: begin
 718                     csr_output_value = time_counter[31:0];
 719                 end
 720                 `csr_instret: begin
 721                     csr_output_value = instret_counter[31:0];
 722                 end
 723                 `csr_cycleh: begin
 724                     csr_output_value = cycle_counter[63:32];
 725                 end
 726                 `csr_timeh: begin
 727                     csr_output_value = time_counter[63:32];
 728                 end
 729                 `csr_instreth: begin
 730                     csr_output_value = instret_counter[63:32];
 731                 end
 732                 `csr_mvendorid: begin
 733                     csr_output_value = mvendorid;
 734                 end
 735                 `csr_marchid: begin
 736                     csr_output_value = marchid;
 737                 end
 738                 `csr_mimpid: begin
 739                     csr_output_value = mimpid;
 740                 end
 741                 `csr_mhartid: begin
 742                     csr_output_value = mhartid;
 743                 end
 744                 `csr_misa: begin
 745                     csr_output_value = misa;
 746                 end
 747                 `csr_mstatus: begin
 748                     csr_output_value = make_mstatus(mstatus_tsr,
 749                                                     mstatus_tw,
 750                                                     mstatus_tvm,
 751                                                     mstatus_mxr,
 752                                                     mstatus_sum,
 753                                                     mstatus_mprv,
 754                                                     mstatus_xs,
 755                                                     mstatus_fs,
 756                                                     mstatus_mpp,
 757                                                     mstatus_spp,
 758                                                     mstatus_mpie,
 759                                                     mstatus_spie,
 760                                                     mstatus_upie,
 761                                                     mstatus_mie,
 762                                                     mstatus_sie,
 763                                                     mstatus_uie);
 764                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 765                     if(csr_writes) begin
 766                         mstatus_mpie = csr_written_value[7];
 767                         mstatus_mie = csr_written_value[3];
 768                     end
 769                 end
 770                 `csr_mie: begin
 771                     csr_output_value = 0;
 772                     csr_output_value[11] = mie_meie;
 773                     csr_output_value[9] = mie_seie;
 774                     csr_output_value[8] = mie_ueie;
 775                     csr_output_value[7] = mie_mtie;
 776                     csr_output_value[5] = mie_stie;
 777                     csr_output_value[4] = mie_utie;
 778                     csr_output_value[3] = mie_msie;
 779                     csr_output_value[1] = mie_ssie;
 780                     csr_output_value[0] = mie_usie;
 781                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 782                     if(csr_writes) begin
 783                         mie_meie = csr_written_value[11];
 784                         mie_mtie = csr_written_value[7];
 785                         mie_msie = csr_written_value[3];
 786                     end
 787                 end
 788                 `csr_mtvec: begin
 789                     csr_output_value = mtvec;
 790                 end
 791                 `csr_mscratch: begin
 792                     csr_output_value = mscratch;
 793                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 794                     if(csr_writes)
 795                         mscratch = csr_written_value;
 796                 end
 797                 `csr_mepc: begin
 798                     csr_output_value = mepc;
 799                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 800                     if(csr_writes)
 801                         mepc = csr_written_value;
 802                 end
 803                 `csr_mcause: begin
 804                     csr_output_value = mcause;
 805                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 806                     if(csr_writes)
 807                         mcause = csr_written_value;
 808                 end
 809                 `csr_mip: begin
 810                     csr_output_value = 0;
 811                     csr_output_value[11] = mip_meip;
 812                     csr_output_value[9] = mip_seip;
 813                     csr_output_value[8] = mip_ueip;
 814                     csr_output_value[7] = mip_mtip;
 815                     csr_output_value[5] = mip_stip;
 816                     csr_output_value[4] = mip_utip;
 817                     csr_output_value[3] = mip_msip;
 818                     csr_output_value[1] = mip_ssip;
 819                     csr_output_value[0] = mip_usip;
 820                 end
 821                 endcase
 822                 if(csr_reads)
 823                     write_register(decoder_rd, csr_output_value);
 824             end
 825             else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
 826                 // do nothing
 827             end
 828         end
 829         endcase
 830     end
 831
 832 endmodule
 833 """
 834