cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 from migen import *
  30 from migen.fhdl import verilog
  31 from migen.fhdl.structure import _Operator
  32
  33 from riscvdefs import *
  34 from cpudefs import *
  35
  36 class MemoryInterface:
  37     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  38     fetch_data = Signal(32, name="memory_interface_fetch_data")
  39     fetch_valid = Signal(name="memory_interface_fetch_valid")
  40     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  41     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  42     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  43     rw_active = Signal(name="memory_interface_rw_active")
  44     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  45     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  46     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  47     rw_wait = Signal(name="memory_interface_rw_wait")
  48
  49
  50 class Decoder:
  51     funct7 = Signal(7, name="decoder_funct7")
  52     funct3 = Signal(3, name="decoder_funct3")
  53     rd = Signal(5, name="decoder_rd")
  54     rs1 = Signal(5, name="decoder_rs1")
  55     rs2 = Signal(5, name="decoder_rs2")
  56     immediate = Signal(32, name="decoder_immediate")
  57     opcode = Signal(7, name="decoder_opcode")
  58     act = Signal(decode_action, name="decoder_action")
  59
  60
  61 class CPU(Module):
  62     """
  63     """
  64
  65     def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
  66         return Case(funct3[:2],
  67                 { F3.sb: ls.eq(Constant(0)),
  68                   F3.sh: ls.eq(load_store_address_low_2[0] != 0),
  69                   F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
  70                   "default": ls.eq(Constant(1))
  71                 })
  72
  73     def get_lsbm(self, dc):
  74         return Cat(Constant(1),
  75                    Mux((dc.funct3[1] | dc.funct3[0]),
  76                        Constant(1), Constant(0)),
  77                    Mux((dc.funct3[1]),
  78                        Constant(0b11, 2), Constant(0, 2)))
  79
  80     def __init__(self):
  81         self.clk = ClockSignal()
  82         self.reset = ResetSignal()
  83         self.tty_write = Signal()
  84         self.tty_write_data = Signal(8)
  85         self.tty_write_busy = Signal()
  86         self.switch_2 = Signal()
  87         self.switch_3 = Signal()
  88         self.led_1 = Signal()
  89         self.led_3 = Signal()
  90
  91         ram_size = Constant(0x8000)
  92         ram_start = Constant(0x10000, 32)
  93         reset_vector = Signal(32)
  94         mtvec = Signal(32)
  95
  96         reset_vector.eq(ram_start)
  97         mtvec.eq(ram_start + 0x40)
  98
  99         l = []
 100         for i in range(31):
 101             l.append(Signal(32, name="register%d" % i))
 102         registers = Array(l)
 103
 104         mi = MemoryInterface()
 105
 106         mii = Instance("cpu_memory_interface", name="memory_instance",
 107                     p_ram_size = ram_size,
 108                     p_ram_start = ram_start,
 109                     i_clk=ClockSignal(),
 110                     i_rst=ResetSignal(),
 111                     i_fetch_address = mi.fetch_address,
 112                     o_fetch_data = mi.fetch_data,
 113                     o_fetch_valid = mi.fetch_valid,
 114                     i_rw_address = mi.rw_address,
 115                     i_rw_byte_mask = mi.rw_byte_mask,
 116                     i_rw_read_not_write = mi.rw_read_not_write,
 117                     i_rw_active = mi.rw_active,
 118                     i_rw_data_in = mi.rw_data_in,
 119                     o_rw_data_out = mi.rw_data_out,
 120                     o_rw_address_valid = mi.rw_address_valid,
 121                     o_rw_wait = mi.rw_wait,
 122                     o_tty_write = self.tty_write,
 123                     o_tty_write_data = self.tty_write_data,
 124                     i_tty_write_busy = self.tty_write_busy,
 125                     i_switch_2 = self.switch_2,
 126                     i_switch_3 = self.switch_3,
 127                     o_led_1 = self.led_1,
 128                     o_led_3 = self.led_3
 129                   )
 130         self.specials += mii
 131
 132         fetch_act = Signal(fetch_action)
 133         fetch_target_pc = Signal(32)
 134         fetch_output_pc = Signal(32)
 135         fetch_output_instruction = Signal(32)
 136         fetch_output_st = Signal(fetch_output_state)
 137
 138         fs = Instance("CPUFetchStage", name="fetch_stage",
 139             i_clk=ClockSignal(),
 140             i_rst=ResetSignal(),
 141             o_memory_interface_fetch_address = mi.fetch_address,
 142             i_memory_interface_fetch_data = mi.fetch_data,
 143             i_memory_interface_fetch_valid = mi.fetch_valid,
 144             i_fetch_action = fetch_act,
 145             i_target_pc = fetch_target_pc,
 146             o_output_pc = fetch_output_pc,
 147             o_output_instruction = fetch_output_instruction,
 148             o_output_state = fetch_output_st,
 149             i_reset_vector = reset_vector,
 150             i_mtvec = mtvec,
 151         )
 152         self.specials += fs
 153
 154         dc = Decoder()
 155
 156         cd = Instance("CPUDecoder", name="decoder",
 157             i_instruction = fetch_output_instruction,
 158             o_funct7 = dc.funct7,
 159             o_funct3 = dc.funct3,
 160             o_rd = dc.rd,
 161             o_rs1 = dc.rs1,
 162             o_rs2 = dc.rs2,
 163             o_immediate = dc.immediate,
 164             o_opcode = dc.opcode,
 165             o_decode_action = dc.act
 166         )
 167         self.specials += cd
 168
 169         register_rs1 = Signal(32)
 170         register_rs2 = Signal(32)
 171         self.comb += If(dc.rs1 == 0,
 172                         register_rs1.eq(0)
 173                      ).Else(
 174                         register_rs1.eq(registers[dc.rs1-1]))
 175         self.comb += If(dc.rs2 == 0,
 176                         register_rs2.eq(0)
 177                      ).Else(
 178                         register_rs2.eq(registers[dc.rs2-1]))
 179
 180         load_store_address = Signal(32)
 181         load_store_address_low_2 = Signal(2)
 182
 183         self.comb += load_store_address.eq(dc.immediate + register_rs1)
 184         self.comb += load_store_address_low_2.eq(
 185                             dc.immediate[:2] + register_rs1[:2])
 186
 187         load_store_misaligned = Signal()
 188
 189         lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3,
 190                                      load_store_address_low_2)
 191         self.comb += lsa
 192
 193         # XXX rwaddr not 31:2 any more
 194         self.comb += mi.rw_address.eq(load_store_address[2:])
 195
 196         unshifted_load_store_byte_mask = Signal(4)
 197
 198         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc))
 199
 200         # XXX yuck.  this will cause migen simulation to fail
 201         # (however conversion to verilog works)
 202         self.comb += mi.rw_byte_mask.eq(
 203                 _Operator("<<", [unshifted_load_store_byte_mask,
 204                                         load_store_address_low_2]))
 205
 206         # XXX not obvious
 207         b3 = Mux(load_store_address_low_2[1],
 208                  Mux(load_store_address_low_2[0], register_rs2[0:8],
 209                                                   register_rs2[8:16]),
 210                  Mux(load_store_address_low_2[0], register_rs2[16:24],
 211                                                   register_rs2[24:32]))
 212         b2 = Mux(load_store_address_low_2[1], register_rs2[0:8],
 213                                               register_rs2[16:24])
 214         b1 = Mux(load_store_address_low_2[0], register_rs2[0:8],
 215                                               register_rs2[8:16])
 216         b0 = register_rs2[0:8]
 217
 218         self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
 219
 220         # XXX not obvious
 221         unmasked_loaded_value = Signal(32)
 222
 223         b0 = Mux(load_store_address_low_2[1],
 224                  Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
 225                                                   mi.rw_data_out[16:24]),
 226                  Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
 227                                                   mi.rw_data_out[0:8]))
 228         b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
 229                                               mi.rw_data_out[8:16])
 230         b23 = mi.rw_data_out[16:32]
 231
 232         self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
 233
 234         # XXX not obvious
 235         loaded_value = Signal(32)
 236
 237         b0 = unmasked_loaded_value[0:8]
 238         b1 = Mux(dc.funct3[0:2] == 0,
 239                 Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8),
 240                 unmasked_loaded_value[8:16])
 241         b2 = Mux(dc.funct3[1] == 0,
 242                 Replicate(~dc.funct3[2] &
 243                            Mux(dc.funct3[0], unmasked_loaded_value[15],
 244                                                   unmasked_loaded_value[7]),
 245                           16),
 246                 unmasked_loaded_value[16:32])
 247
 248         self.comb += loaded_value.eq(Cat(b0, b1, b2))
 249
 250         self.comb += mi.rw_active.eq(~self.reset
 251                         & (fetch_output_st == fetch_output_state_valid)
 252                         & ~load_store_misaligned
 253                         & ((dc.act & (DA.load | DA.store)) != 0))
 254
 255         self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
 256
 257         # alu
 258         alu_a = Signal(32)
 259         alu_b = Signal(32)
 260         alu_result = Signal(32)
 261
 262         self.comb += alu_a.eq(register_rs1)
 263         self.comb += alu_b.eq(Mux(dc.opcode[5],
 264                                   register_rs2,
 265                                   dc.immediate))
 266
 267         ali = Instance("cpu_alu", name="alu",
 268             i_funct7 = dc.funct7,
 269             i_funct3 = dc.funct3,
 270             i_opcode = dc.opcode,
 271             i_a = alu_a,
 272             i_b = alu_b,
 273             o_result = alu_result
 274         )
 275         self.specials += ali
 276
 277
 278 if __name__ == "__main__":
 279     example = CPU()
 280     print(verilog.convert(example,
 281          {
 282            example.tty_write,
 283            example.tty_write_data,
 284            example.tty_write_busy,
 285            example.switch_2,
 286            example.switch_3,
 287            example.led_1,
 288            example.led_3,
 289            }))
 290
 291 """
 292
 293     wire [31:0] lui_auipc_result = decoder_opcode[5] ? decoder_immediate : decoder_immediate + fetch_output_pc;
 294
 295     assign fetch_target_pc[31:1] = ((decoder_opcode != `opcode_jalr ? fetch_output_pc[31:1] : register_rs1[31:1]) + decoder_immediate[31:1]);
 296     assign fetch_target_pc[0] = 0;
 297
 298     wire misaligned_jump_target = fetch_target_pc[1];
 299
 300     wire [31:0] branch_arg_a = {register_rs1[31] ^ ~decoder_funct3[1], register_rs1[30:0]};
 301     wire [31:0] branch_arg_b = {register_rs2[31] ^ ~decoder_funct3[1], register_rs2[30:0]};
 302
 303     wire branch_taken = decoder_funct3[0] ^ (decoder_funct3[2] ? branch_arg_a < branch_arg_b : branch_arg_a == branch_arg_b);
 304
 305     reg [31:0] mcause = 0;
 306     reg [31:0] mepc = 32'hXXXXXXXX;
 307     reg [31:0] mscratch = 32'hXXXXXXXX;
 308
 309     reg mstatus_mpie = 1'bX;
 310     reg mstatus_mie = 0;
 311     parameter mstatus_mprv = 0;
 312     parameter mstatus_tsr = 0;
 313     parameter mstatus_tw = 0;
 314     parameter mstatus_tvm = 0;
 315     parameter mstatus_mxr = 0;
 316     parameter mstatus_sum = 0;
 317     parameter mstatus_xs = 0;
 318     parameter mstatus_fs = 0;
 319     parameter mstatus_mpp = 2'b11;
 320     parameter mstatus_spp = 0;
 321     parameter mstatus_spie = 0;
 322     parameter mstatus_upie = 0;
 323     parameter mstatus_sie = 0;
 324     parameter mstatus_uie = 0;
 325
 326     reg mie_meie = 1'bX;
 327     reg mie_mtie = 1'bX;
 328     reg mie_msie = 1'bX;
 329     parameter mie_seie = 0;
 330     parameter mie_ueie = 0;
 331     parameter mie_stie = 0;
 332     parameter mie_utie = 0;
 333     parameter mie_ssie = 0;
 334     parameter mie_usie = 0;
 335
 336     task reset_to_initial;
 337     begin
 338         mcause = 0;
 339         mepc = 32'hXXXXXXXX;
 340         mscratch = 32'hXXXXXXXX;
 341         mstatus_mie = 0;
 342         mstatus_mpie = 1'bX;
 343         mie_meie = 1'bX;
 344         mie_mtie = 1'bX;
 345         mie_msie = 1'bX;
 346         registers['h01] <= 32'hXXXXXXXX;
 347         registers['h02] <= 32'hXXXXXXXX;
 348         registers['h03] <= 32'hXXXXXXXX;
 349         registers['h04] <= 32'hXXXXXXXX;
 350         registers['h05] <= 32'hXXXXXXXX;
 351         registers['h06] <= 32'hXXXXXXXX;
 352         registers['h07] <= 32'hXXXXXXXX;
 353         registers['h08] <= 32'hXXXXXXXX;
 354         registers['h09] <= 32'hXXXXXXXX;
 355         registers['h0A] <= 32'hXXXXXXXX;
 356         registers['h0B] <= 32'hXXXXXXXX;
 357         registers['h0C] <= 32'hXXXXXXXX;
 358         registers['h0D] <= 32'hXXXXXXXX;
 359         registers['h0E] <= 32'hXXXXXXXX;
 360         registers['h0F] <= 32'hXXXXXXXX;
 361         registers['h10] <= 32'hXXXXXXXX;
 362         registers['h11] <= 32'hXXXXXXXX;
 363         registers['h12] <= 32'hXXXXXXXX;
 364         registers['h13] <= 32'hXXXXXXXX;
 365         registers['h14] <= 32'hXXXXXXXX;
 366         registers['h15] <= 32'hXXXXXXXX;
 367         registers['h16] <= 32'hXXXXXXXX;
 368         registers['h17] <= 32'hXXXXXXXX;
 369         registers['h18] <= 32'hXXXXXXXX;
 370         registers['h19] <= 32'hXXXXXXXX;
 371         registers['h1A] <= 32'hXXXXXXXX;
 372         registers['h1B] <= 32'hXXXXXXXX;
 373         registers['h1C] <= 32'hXXXXXXXX;
 374         registers['h1D] <= 32'hXXXXXXXX;
 375         registers['h1E] <= 32'hXXXXXXXX;
 376         registers['h1F] <= 32'hXXXXXXXX;
 377     end
 378     endtask
 379
 380     task write_register(input [4:0] register_number, input [31:0] value);
 381     begin
 382         if(register_number != 0)
 383             registers[register_number] <= value;
 384     end
 385     endtask
 386
 387     function [31:0] evaluate_csr_funct3_operation(input [2:0] funct3, input [31:0] previous_value, input [31:0] written_value);
 388     begin
 389         case(funct3)
 390         `funct3_csrrw, `funct3_csrrwi:
 391             evaluate_csr_funct3_operation = written_value;
 392         `funct3_csrrs, `funct3_csrrsi:
 393             evaluate_csr_funct3_operation = written_value | previous_value;
 394         `funct3_csrrc, `funct3_csrrci:
 395             evaluate_csr_funct3_operation = ~written_value & previous_value;
 396         default:
 397             evaluate_csr_funct3_operation = 32'hXXXXXXXX;
 398         endcase
 399     end
 400     endfunction
 401
 402     parameter misa_a = 1'b0;
 403     parameter misa_b = 1'b0;
 404     parameter misa_c = 1'b0;
 405     parameter misa_d = 1'b0;
 406     parameter misa_e = 1'b0;
 407     parameter misa_f = 1'b0;
 408     parameter misa_g = 1'b0;
 409     parameter misa_h = 1'b0;
 410     parameter misa_i = 1'b1;
 411     parameter misa_j = 1'b0;
 412     parameter misa_k = 1'b0;
 413     parameter misa_l = 1'b0;
 414     parameter misa_m = 1'b0;
 415     parameter misa_n = 1'b0;
 416     parameter misa_o = 1'b0;
 417     parameter misa_p = 1'b0;
 418     parameter misa_q = 1'b0;
 419     parameter misa_r = 1'b0;
 420     parameter misa_s = 1'b0;
 421     parameter misa_t = 1'b0;
 422     parameter misa_u = 1'b0;
 423     parameter misa_v = 1'b0;
 424     parameter misa_w = 1'b0;
 425     parameter misa_x = 1'b0;
 426     parameter misa_y = 1'b0;
 427     parameter misa_z = 1'b0;
 428     parameter misa = {
 429         2'b01,
 430         4'b0,
 431         misa_z,
 432         misa_y,
 433         misa_x,
 434         misa_w,
 435         misa_v,
 436         misa_u,
 437         misa_t,
 438         misa_s,
 439         misa_r,
 440         misa_q,
 441         misa_p,
 442         misa_o,
 443         misa_n,
 444         misa_m,
 445         misa_l,
 446         misa_k,
 447         misa_j,
 448         misa_i,
 449         misa_h,
 450         misa_g,
 451         misa_f,
 452         misa_e,
 453         misa_d,
 454         misa_c,
 455         misa_b,
 456         misa_a};
 457
 458     parameter mvendorid = 32'b0;
 459     parameter marchid = 32'b0;
 460     parameter mimpid = 32'b0;
 461     parameter mhartid = 32'b0;
 462
 463     function [31:0] make_mstatus(input mstatus_tsr,
 464         input mstatus_tw,
 465         input mstatus_tvm,
 466         input mstatus_mxr,
 467         input mstatus_sum,
 468         input mstatus_mprv,
 469         input [1:0] mstatus_xs,
 470         input [1:0] mstatus_fs,
 471         input [1:0] mstatus_mpp,
 472         input mstatus_spp,
 473         input mstatus_mpie,
 474         input mstatus_spie,
 475         input mstatus_upie,
 476         input mstatus_mie,
 477         input mstatus_sie,
 478         input mstatus_uie);
 479     begin
 480         make_mstatus = {(mstatus_xs == 2'b11) | (mstatus_fs == 2'b11),
 481             8'b0,
 482             mstatus_tsr,
 483             mstatus_tw,
 484             mstatus_tvm,
 485             mstatus_mxr,
 486             mstatus_sum,
 487             mstatus_mprv,
 488             mstatus_xs,
 489             mstatus_fs,
 490             mstatus_mpp,
 491             2'b0,
 492             mstatus_spp,
 493             mstatus_mpie,
 494             1'b0,
 495             mstatus_spie,
 496             mstatus_upie,
 497             mstatus_mie,
 498             1'b0,
 499             mstatus_sie,
 500             mstatus_uie};
 501     end
 502     endfunction
 503
 504     wire mip_meip = 0; // TODO: implement external interrupts
 505     parameter mip_seip = 0;
 506     parameter mip_ueip = 0;
 507     wire mip_mtip = 0; // TODO: implement timer interrupts
 508     parameter mip_stip = 0;
 509     parameter mip_utip = 0;
 510     parameter mip_msip = 0;
 511     parameter mip_ssip = 0;
 512     parameter mip_usip = 0;
 513
 514     wire csr_op_is_valid;
 515
 516     function `fetch_action get_fetch_action(
 517         input `fetch_output_state fetch_output_state,
 518         input `decode_action decode_action,
 519         input load_store_misaligned,
 520         input memory_interface_rw_address_valid,
 521         input memory_interface_rw_wait,
 522         input branch_taken,
 523         input misaligned_jump_target,
 524         input csr_op_is_valid
 525         );
 526     begin
 527         case(fetch_output_state)
 528         `fetch_output_state_empty:
 529             get_fetch_action = `fetch_action_default;
 530         `fetch_output_state_trap:
 531             get_fetch_action = `fetch_action_ack_trap;
 532         `fetch_output_state_valid: begin
 533             if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 534                 get_fetch_action = `fetch_action_error_trap;
 535             end
 536             else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 537                 get_fetch_action = `fetch_action_noerror_trap;
 538             end
 539             else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
 540                 if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
 541                     get_fetch_action = `fetch_action_error_trap;
 542                 end
 543                 else if(memory_interface_rw_wait) begin
 544                     get_fetch_action = `fetch_action_wait;
 545                 end
 546                 else begin
 547                     get_fetch_action = `fetch_action_default;
 548                 end
 549             end
 550             else if((decode_action & `decode_action_fence_i) != 0) begin
 551                 get_fetch_action = `fetch_action_fence;
 552             end
 553             else if((decode_action & `decode_action_branch) != 0) begin
 554                 if(branch_taken) begin
 555                     if(misaligned_jump_target) begin
 556                         get_fetch_action = `fetch_action_error_trap;
 557                     end
 558                     else begin
 559                         get_fetch_action = `fetch_action_jump;
 560                     end
 561                 end
 562                 else
 563                 begin
 564                     get_fetch_action = `fetch_action_default;
 565                 end
 566             end
 567             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 568                 if(misaligned_jump_target) begin
 569                     get_fetch_action = `fetch_action_error_trap;
 570                 end
 571                 else begin
 572                     get_fetch_action = `fetch_action_jump;
 573                 end
 574             end
 575             else if((decode_action & `decode_action_csr) != 0) begin
 576                 if(csr_op_is_valid)
 577                     get_fetch_action = `fetch_action_default;
 578                 else
 579                     get_fetch_action = `fetch_action_error_trap;
 580             end
 581             else begin
 582                 get_fetch_action = `fetch_action_default;
 583             end
 584         end
 585         default:
 586             get_fetch_action = 32'hXXXXXXXX;
 587         endcase
 588     end
 589     endfunction
 590
 591     assign fetch_action = get_fetch_action(
 592         fetch_output_state,
 593         decode_action,
 594         load_store_misaligned,
 595         memory_interface_rw_address_valid,
 596         memory_interface_rw_wait,
 597         branch_taken,
 598         misaligned_jump_target,
 599         csr_op_is_valid
 600         );
 601
 602     task handle_trap;
 603     begin
 604         mstatus_mpie = mstatus_mie;
 605         mstatus_mie = 0;
 606         mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc;
 607         if(fetch_action == `fetch_action_ack_trap) begin
 608             mcause = `cause_instruction_access_fault;
 609         end
 610         else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
 611             mcause = `cause_illegal_instruction;
 612         end
 613         else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
 614             mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint;
 615         end
 616         else if((decode_action & `decode_action_load) != 0) begin
 617             if(load_store_misaligned)
 618                 mcause = `cause_load_address_misaligned;
 619             else
 620                 mcause = `cause_load_access_fault;
 621         end
 622         else if((decode_action & `decode_action_store) != 0) begin
 623             if(load_store_misaligned)
 624                 mcause = `cause_store_amo_address_misaligned;
 625             else
 626                 mcause = `cause_store_amo_access_fault;
 627         end
 628         else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin
 629             mcause = `cause_instruction_address_misaligned;
 630         end
 631         else begin
 632             mcause = `cause_illegal_instruction;
 633         end
 634     end
 635     endtask
 636
 637     wire [11:0] csr_number = decoder_immediate;
 638     wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1;
 639     wire csr_reads = decoder_funct3[1] | (decoder_rd != 0);
 640     wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0);
 641
 642     function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes);
 643     begin
 644         case(csr_number)
 645         `csr_ustatus,
 646         `csr_fflags,
 647         `csr_frm,
 648         `csr_fcsr,
 649         `csr_uie,
 650         `csr_utvec,
 651         `csr_uscratch,
 652         `csr_uepc,
 653         `csr_ucause,
 654         `csr_utval,
 655         `csr_uip,
 656         `csr_sstatus,
 657         `csr_sedeleg,
 658         `csr_sideleg,
 659         `csr_sie,
 660         `csr_stvec,
 661         `csr_scounteren,
 662         `csr_sscratch,
 663         `csr_sepc,
 664         `csr_scause,
 665         `csr_stval,
 666         `csr_sip,
 667         `csr_satp,
 668         `csr_medeleg,
 669         `csr_mideleg,
 670         `csr_dcsr,
 671         `csr_dpc,
 672         `csr_dscratch:
 673             get_csr_op_is_valid = 0;
 674         `csr_cycle,
 675         `csr_time,
 676         `csr_instret,
 677         `csr_cycleh,
 678         `csr_timeh,
 679         `csr_instreth,
 680         `csr_mvendorid,
 681         `csr_marchid,
 682         `csr_mimpid,
 683         `csr_mhartid:
 684             get_csr_op_is_valid = ~csr_writes;
 685         `csr_misa,
 686         `csr_mstatus,
 687         `csr_mie,
 688         `csr_mtvec,
 689         `csr_mscratch,
 690         `csr_mepc,
 691         `csr_mcause,
 692         `csr_mip:
 693             get_csr_op_is_valid = 1;
 694         `csr_mcounteren,
 695         `csr_mtval,
 696         `csr_mcycle,
 697         `csr_minstret,
 698         `csr_mcycleh,
 699         `csr_minstreth:
 700             // TODO: CSRs not implemented yet
 701             get_csr_op_is_valid = 0;
 702         endcase
 703     end
 704     endfunction
 705
 706     assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes);
 707
 708     wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
 709     wire [63:0] time_counter = 0; // TODO: implement time_counter
 710     wire [63:0] instret_counter = 0; // TODO: implement instret_counter
 711
 712     always @(posedge clk) begin:main_block
 713         if(reset) begin
 714             reset_to_initial();
 715             disable main_block;
 716         end
 717         case(fetch_output_state)
 718         `fetch_output_state_empty: begin
 719         end
 720         `fetch_output_state_trap: begin
 721             handle_trap();
 722         end
 723         `fetch_output_state_valid: begin:valid
 724             if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
 725                 handle_trap();
 726             end
 727             else if((decode_action & `decode_action_load) != 0) begin
 728                 if(~memory_interface_rw_wait)
 729                     write_register(decoder_rd, loaded_value);
 730             end
 731             else if((decode_action & `decode_action_op_op_imm) != 0) begin
 732                 write_register(decoder_rd, alu_result);
 733             end
 734             else if((decode_action & `decode_action_lui_auipc) != 0) begin
 735                 write_register(decoder_rd, lui_auipc_result);
 736             end
 737             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 738                 write_register(decoder_rd, fetch_output_pc + 4);
 739             end
 740             else if((decode_action & `decode_action_csr) != 0) begin:csr
 741                 reg [31:0] csr_output_value;
 742                 reg [31:0] csr_written_value;
 743                 csr_output_value = 32'hXXXXXXXX;
 744                 csr_written_value = 32'hXXXXXXXX;
 745                 case(csr_number)
 746                 `csr_cycle: begin
 747                     csr_output_value = cycle_counter[31:0];
 748                 end
 749                 `csr_time: begin
 750                     csr_output_value = time_counter[31:0];
 751                 end
 752                 `csr_instret: begin
 753                     csr_output_value = instret_counter[31:0];
 754                 end
 755                 `csr_cycleh: begin
 756                     csr_output_value = cycle_counter[63:32];
 757                 end
 758                 `csr_timeh: begin
 759                     csr_output_value = time_counter[63:32];
 760                 end
 761                 `csr_instreth: begin
 762                     csr_output_value = instret_counter[63:32];
 763                 end
 764                 `csr_mvendorid: begin
 765                     csr_output_value = mvendorid;
 766                 end
 767                 `csr_marchid: begin
 768                     csr_output_value = marchid;
 769                 end
 770                 `csr_mimpid: begin
 771                     csr_output_value = mimpid;
 772                 end
 773                 `csr_mhartid: begin
 774                     csr_output_value = mhartid;
 775                 end
 776                 `csr_misa: begin
 777                     csr_output_value = misa;
 778                 end
 779                 `csr_mstatus: begin
 780                     csr_output_value = make_mstatus(mstatus_tsr,
 781                                                     mstatus_tw,
 782                                                     mstatus_tvm,
 783                                                     mstatus_mxr,
 784                                                     mstatus_sum,
 785                                                     mstatus_mprv,
 786                                                     mstatus_xs,
 787                                                     mstatus_fs,
 788                                                     mstatus_mpp,
 789                                                     mstatus_spp,
 790                                                     mstatus_mpie,
 791                                                     mstatus_spie,
 792                                                     mstatus_upie,
 793                                                     mstatus_mie,
 794                                                     mstatus_sie,
 795                                                     mstatus_uie);
 796                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 797                     if(csr_writes) begin
 798                         mstatus_mpie = csr_written_value[7];
 799                         mstatus_mie = csr_written_value[3];
 800                     end
 801                 end
 802                 `csr_mie: begin
 803                     csr_output_value = 0;
 804                     csr_output_value[11] = mie_meie;
 805                     csr_output_value[9] = mie_seie;
 806                     csr_output_value[8] = mie_ueie;
 807                     csr_output_value[7] = mie_mtie;
 808                     csr_output_value[5] = mie_stie;
 809                     csr_output_value[4] = mie_utie;
 810                     csr_output_value[3] = mie_msie;
 811                     csr_output_value[1] = mie_ssie;
 812                     csr_output_value[0] = mie_usie;
 813                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 814                     if(csr_writes) begin
 815                         mie_meie = csr_written_value[11];
 816                         mie_mtie = csr_written_value[7];
 817                         mie_msie = csr_written_value[3];
 818                     end
 819                 end
 820                 `csr_mtvec: begin
 821                     csr_output_value = mtvec;
 822                 end
 823                 `csr_mscratch: begin
 824                     csr_output_value = mscratch;
 825                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 826                     if(csr_writes)
 827                         mscratch = csr_written_value;
 828                 end
 829                 `csr_mepc: begin
 830                     csr_output_value = mepc;
 831                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 832                     if(csr_writes)
 833                         mepc = csr_written_value;
 834                 end
 835                 `csr_mcause: begin
 836                     csr_output_value = mcause;
 837                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 838                     if(csr_writes)
 839                         mcause = csr_written_value;
 840                 end
 841                 `csr_mip: begin
 842                     csr_output_value = 0;
 843                     csr_output_value[11] = mip_meip;
 844                     csr_output_value[9] = mip_seip;
 845                     csr_output_value[8] = mip_ueip;
 846                     csr_output_value[7] = mip_mtip;
 847                     csr_output_value[5] = mip_stip;
 848                     csr_output_value[4] = mip_utip;
 849                     csr_output_value[3] = mip_msip;
 850                     csr_output_value[1] = mip_ssip;
 851                     csr_output_value[0] = mip_usip;
 852                 end
 853                 endcase
 854                 if(csr_reads)
 855                     write_register(decoder_rd, csr_output_value);
 856             end
 857             else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
 858                 // do nothing
 859             end
 860         end
 861         endcase
 862     end
 863
 864 endmodule
 865 """
 866