cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 import string
  30 from migen import *
  31 from migen.fhdl import verilog
  32 from migen.fhdl.structure import _Operator
  33
  34 from riscvdefs import *
  35 from cpudefs import *
  36
  37 class MemoryInterface:
  38     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  39     fetch_data = Signal(32, name="memory_interface_fetch_data")
  40     fetch_valid = Signal(name="memory_interface_fetch_valid")
  41     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  42     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  43     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  44     rw_active = Signal(name="memory_interface_rw_active")
  45     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  46     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  47     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  48     rw_wait = Signal(name="memory_interface_rw_wait")
  49
  50
  51 class Decoder:
  52     funct7 = Signal(7, name="decoder_funct7")
  53     funct3 = Signal(3, name="decoder_funct3")
  54     rd = Signal(5, name="decoder_rd")
  55     rs1 = Signal(5, name="decoder_rs1")
  56     rs2 = Signal(5, name="decoder_rs2")
  57     immediate = Signal(32, name="decoder_immediate")
  58     opcode = Signal(7, name="decoder_opcode")
  59     act = Signal(decode_action, name="decoder_action")
  60
  61 class MStatus:
  62     def __init__(self, comb, sync):
  63         self.comb = comb
  64         self.sync = sync
  65         self.mpie = Signal(name="mstatus_mpie")
  66         self.mie = Signal(name="mstatus_mie")
  67         self.mprv = Signal(name="mstatus_mprv")
  68         self.tsr = Signal(name="mstatus_tsr")
  69         self.tw = Signal(name="mstatus_tw")
  70         self.tvm = Signal(name="mstatus_tvm")
  71         self.mxr = Signal(name="mstatus_mxr")
  72         self._sum = Signal(name="mstatus_sum")
  73         self.xs = Signal(name="mstatus_xs")
  74         self.fs = Signal(name="mstatus_fs")
  75         self.mpp = Signal(2, name="mstatus_mpp")
  76         self.spp = Signal(name="mstatus_spp")
  77         self.spie = Signal(name="mstatus_spie")
  78         self.upie = Signal(name="mstatus_upie")
  79         self.sie = Signal(name="mstatus_sie")
  80         self.uie = Signal(name="mstatus_uie")
  81
  82         for n in dir(self):
  83             if n in ['make', 'mpp', 'comb', 'sync'] or n.startswith("_"):
  84                 continue
  85             self.comb += getattr(self, n).eq(0x0)
  86         self.comb += self.mpp.eq(0b11)
  87
  88         self.sync += self.mie.eq(0)
  89         self.sync += self.mpie.eq(0)
  90
  91     def make(self):
  92         return Cat(
  93                 self.uie, self.sie, Constant(0), self.mie,
  94                 self.upie, self.spie, Constant(0), self.mpie,
  95                 self.spp, Constant(0, 2), self.mpp,
  96                 self.fs, self.xs, self.mprv, self._sum,
  97                 self.mxr, self.tvm, self.tw, self.tsr,
  98                 Constant(0, 8),
  99                 (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2))
 100                 )
 101
 102
 103 class MIE:
 104     def __init__(self, comb, sync):
 105         self.comb = comb
 106         self.sync = sync
 107         self.meie = Signal(name="mie_meie")
 108         self.mtie = Signal(name="mie_mtie")
 109         self.msie = Signal(name="mie_msie")
 110         self.ueie = Signal(name="mie_ueie")
 111         self.stie = Signal(name="mie_stie")
 112         self.utie = Signal(name="mie_utie")
 113         self.ssie = Signal(name="mie_ssie")
 114         self.usie = Signal(name="mie_usie")
 115
 116         for n in dir(self):
 117             if n in ['make', 'comb', 'sync'] or n.startswith("_"):
 118                 continue
 119             self.comb += getattr(self, n).eq(0x0)
 120
 121         self.sync += self.meie.eq(0)
 122         self.sync += self.mtie.eq(0)
 123         self.sync += self.msie.eq(0)
 124
 125 class MIP:
 126     def __init__(self, comb, sync):
 127         self.comb = comb
 128         self.sync = sync
 129         self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts
 130         self.seip = Signal(name="mip_seip")
 131         self.ueip = Signal(name="mip_uiep")
 132         self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts
 133         self.stip = Signal(name="mip_stip")
 134         self.msip = Signal(name="mip_stip")
 135         self.utip = Signal(name="mip_utip")
 136         self.ssip = Signal(name="mip_ssip")
 137         self.usip = Signal(name="mip_usip")
 138
 139         for n in dir(self):
 140             if n in ['comb', 'sync'] or n.startswith("_"):
 141                 continue
 142             self.comb += getattr(self, n).eq(0x0)
 143
 144
 145 class M:
 146     def __init__(self, comb, sync):
 147         self.comb = comb
 148         self.sync = sync
 149         self.mcause = Signal(32)
 150         self.mepc = Signal(32)
 151         self.mscratch = Signal(32)
 152         self.sync += self.mcause.eq(0)
 153         self.sync += self.mepc.eq(0) # 32'hXXXXXXXX;
 154         self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
 155
 156
 157 class Misa:
 158     def __init__(self, comb, sync):
 159         self.comb = comb
 160         self.sync = sync
 161         self.misa = Signal(32)
 162         cl = []
 163         for l in list(string.ascii_lowercase):
 164             value = 1 if l == 'i' else 0
 165             cl.append(Constant(value))
 166         cl.append(Constant(0, 4))
 167         cl.append(Constant(0b01, 2))
 168         self.comb += self.misa.eq(Cat(cl))
 169
 170
 171 class Fetch:
 172     def __init__(self, comb, sync):
 173         self.comb = comb
 174         self.sync = sync
 175         self.action = Signal(fetch_action, name="fetch_action")
 176         self.target_pc = Signal(32, name="fetch_target_pc")
 177         self.output_pc = Signal(32, name="fetch_output_pc")
 178         self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
 179         self.output_state = Signal(fetch_output_state,name="fetch_output_state")
 180
 181     def get_fetch_action(self, dc, load_store_misaligned, mi,
 182                          branch_taken, misaligned_jump_target,
 183                          csr_op_is_valid):
 184         c = {}
 185         c["default"] = self.action.eq(FA.default) # XXX should be 32'XXXXXXXX?
 186         c[FOS.empty] = self.action.eq(FA.default)
 187         c[FOS.trap] = self.action.eq(FA.ack_trap)
 188
 189         # illegal instruction -> error trap
 190         i= If((dc.act & DA.trap_illegal_instruction) != 0,
 191                  self.action.eq(FA.error_trap)
 192               )
 193
 194         # ecall / ebreak -> noerror trap
 195         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
 196                  self.action.eq(FA.noerror_trap))
 197
 198         # load/store: check alignment, check wait
 199         i = i.Elif((dc.act & (DA.load | DA.store)) != 0,
 200                 If((load_store_misaligned | ~mi.rw_address_valid),
 201                     self.action.eq(FA.error_trap) # misaligned or invalid addr
 202                 ).Elif(mi.rw_wait,
 203                     self.action.eq(FA.wait) # wait
 204                 ).Else(
 205                     self.action.eq(FA.default) # ok
 206                 )
 207               )
 208
 209         # fence
 210         i = i.Elif((dc.act & DA.fence) != 0,
 211                  self.action.eq(FA.fence))
 212
 213         # branch -> misaligned=error, otherwise jump
 214         i = i.Elif((dc.act & DA.branch) != 0,
 215                 If(misaligned_jump_target,
 216                     self.action.eq(FA.error_trap)
 217                 ).Else(
 218                     self.action.eq(FA.jump)
 219                 )
 220               )
 221
 222         # jal/jalr -> misaligned=error, otherwise jump
 223         i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
 224                 If(misaligned_jump_target,
 225                     self.action.eq(FA.error_trap)
 226                 ).Else(
 227                     self.action.eq(FA.jump)
 228                 )
 229               )
 230
 231         # csr -> opvalid=ok, else error trap
 232         i = i.Elif((dc.act & DA.csr) != 0,
 233                 If(csr_op_is_valid,
 234                     self.action.eq(FA.default)
 235                 ).Else(
 236                     self.action.eq(FA.error_trap)
 237                 )
 238               )
 239
 240         c[FOS.valid] = i
 241
 242         return Case(self.output_state, c)
 243
 244 class CSR:
 245     def __init__(self, comb, sync, dc, register_rs1):
 246         self.comb = comb
 247         self.sync = sync
 248         self.number = Signal(12, name="csr_number")
 249         self.input_value = Signal(32, name="csr_input_value")
 250         self.reads = Signal(name="csr_reads")
 251         self.writes = Signal(name="csr_writes")
 252         self.op_is_valid = Signal(name="csr_op_is_valid")
 253
 254         self.comb += self.number.eq(dc.immediate)
 255         self.comb += self.input_value.eq(Mux(dc.funct3[2],
 256                                             dc.rs1,
 257                                             register_rs1))
 258         self.comb += self.reads.eq(dc.funct3[1] | (dc.rd != 0))
 259         self.comb += self.writes.eq(~dc.funct3[1] | (dc.rs1 != 0))
 260
 261         self.comb += self.get_csr_op_is_valid()
 262
 263     def get_csr_op_is_valid(self):
 264         """ determines if a CSR is valid
 265         """
 266         c = {}
 267         # invalid csrs
 268         for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr,
 269                   csr_uie, csr_utvec, csr_uscratch, csr_uepc,
 270                   csr_ucause, csr_utval, csr_uip, csr_sstatus,
 271                   csr_sedeleg, csr_sideleg, csr_sie, csr_stvec,
 272                   csr_scounteren, csr_sscratch, csr_sepc, csr_scause,
 273                   csr_stval, csr_sip, csr_satp, csr_medeleg,
 274                   csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]:
 275             c[f] = self.op_is_valid.eq(0)
 276
 277         # not-writeable -> ok
 278         for f in [csr_cycle, csr_time, csr_instret, csr_cycleh,
 279                   csr_timeh, csr_instreth, csr_mvendorid, csr_marchid,
 280                   csr_mimpid, csr_mhartid]:
 281             c[f] = self.op_is_valid.eq(~self.writes)
 282
 283         # valid csrs
 284         for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec,
 285                   csr_mscratch, csr_mepc, csr_mcause, csr_mip]:
 286             c[f] = self.op_is_valid.eq(1)
 287
 288         # not implemented / default
 289         for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret,
 290                   csr_mcycleh, csr_minstreth, "default"]:
 291             c[f] = self.op_is_valid.eq(0)
 292
 293         return Case(self.number, c)
 294
 295     def evaluate_csr_funct3_op(self, funct3, previous, written):
 296         c = { "default": written.eq(Constant(0, 32))}
 297         for f in [F3.csrrw, F3.csrrwi]:
 298             c[f] = written.eq(self.input_value)
 299         for f in [F3.csrrs, F3.csrrsi]:
 300             c[f] = written.eq(self.input_value | previous)
 301         for f in [F3.csrrc, F3.csrrci]:
 302             c[f] = written.eq(~self.input_value & previous)
 303         return Case(funct3, c)
 304
 305
 306 class MInfo:
 307     def __init__(self, comb):
 308         self.comb = comb
 309         # TODO
 310         self.cycle_counter   = Signal(64); # TODO: implement cycle_counter
 311         self.time_counter    = Signal(64); # TODO: implement time_counter
 312         self.instret_counter = Signal(64); # TODO: implement instret_counter
 313
 314         self.mvendorid = Signal(32)
 315         self.marchid = Signal(32)
 316         self.mimpid = Signal(32)
 317         self.mhartid = Signal(32)
 318         self.comb += self.mvendorid.eq(Constant(0, 32))
 319         self.comb += self.marchid.eq(Constant(0, 32))
 320         self.comb += self.mimpid.eq(Constant(0, 32))
 321         self.comb += self.mhartid.eq(Constant(0, 32))
 322
 323
 324 class CPU(Module):
 325     """
 326     """
 327
 328     def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
 329         """ returns whether a load/store is misaligned
 330         """
 331         return Case(funct3[:2],
 332                 { F3.sb: ls.eq(Constant(0)),
 333                   F3.sh: ls.eq(load_store_address_low_2[0] != 0),
 334                   F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
 335                   "default": ls.eq(Constant(1))
 336                 })
 337
 338     def get_lsbm(self, dc):
 339         return Cat(Constant(1),
 340                    Mux((dc.funct3[1] | dc.funct3[0]),
 341                        Constant(1), Constant(0)),
 342                    Mux((dc.funct3[1]),
 343                        Constant(0b11, 2), Constant(0, 2)))
 344
 345     # XXX this happens to get done by various self.sync actions
 346     #def reset_to_initial(self, m, mstatus, mie, registers):
 347     #    return [m.mcause.eq(0),
 348     #            ]
 349
 350     def write_register(self, register_number, value):
 351         return If(register_number != 0,
 352                   self.registers[register_number].eq(value)
 353                )
 354
 355     def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
 356         s = [ms.mpie.eq(ms.mie),
 357              ms.mie.eq(0),
 358              m.mepc.eq(Mux(ft.action == FA.noerror_trap,
 359                            ft.output_pc + 4,
 360                            ft.output_pc))]
 361
 362         # fetch action ack trap
 363         i = If(ft.action == FA.ack_trap,
 364                 m.mcause.eq(cause_instruction_access_fault)
 365               )
 366
 367         # ecall/ebreak
 368         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
 369                 m.mcause.eq(Mux(dc.immediate[0],
 370                                 cause_machine_environment_call,
 371                                 cause_breakpoint))
 372               )
 373
 374         # load
 375         i = i.Elif((dc.act & DA.load) != 0,
 376                 If(load_store_misaligned,
 377                     m.mcause.eq(cause_load_address_misaligned)
 378                 ).Else(
 379                     m.mcause.eq(cause_load_access_fault)
 380                 )
 381               )
 382
 383         # store
 384         i = i.Elif((dc.act & DA.store) != 0,
 385                 If(load_store_misaligned,
 386                     m.mcause.eq(cause_store_amo_address_misaligned)
 387                 ).Else(
 388                     m.mcause.eq(cause_store_amo_access_fault)
 389                 )
 390               )
 391
 392         # jal/jalr -> misaligned=error, otherwise jump
 393         i = i.Elif((dc.act & (DA.jal | DA.jalr | DA.branch)) != 0,
 394                 m.mcause.eq(cause_instruction_address_misaligned)
 395               )
 396
 397         # defaults to illegal instruction
 398         i = i.Else(m.mcause.eq(cause_illegal_instruction))
 399
 400         s.append(i)
 401         return s
 402
 403     def main_block(self, minfo, misa, csr, mi, m, mstatus, ft, dc,
 404                          load_store_misaligned,
 405                          loaded_value, alu_result,
 406                          lui_auipc_result):
 407         c = {}
 408         c[FOS.empty] = []
 409         c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc,
 410                                        load_store_misaligned)
 411         c[FOS.valid] = self.handle_valid(minfo, misa, csr, mi, m, mstatus, ft, dc,
 412                                        load_store_misaligned,
 413                                        loaded_value,
 414                                        alu_result,
 415                                        lui_auipc_result)
 416         return Case(ft.output_state, c)
 417
 418     def handle_valid(self, minfo, misa, csr, mi, m, mstatus, ft, dc,
 419                            load_store_misaligned,
 420                            loaded_value, alu_result,
 421                            lui_auipc_result):
 422         # fetch action ack trap
 423         i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
 424                 self.handle_trap(m, mstatus, ft, dc,
 425                                        load_store_misaligned)
 426               )
 427
 428         # load
 429         i = i.Elif((dc.act & DA.load) != 0,
 430                 If(~mi.rw_wait,
 431                     self.write_register(dc.rd, loaded_value)
 432                 )
 433               )
 434
 435         # op or op_immediate
 436         i = i.Elif((dc.act & DA.op_op_imm) != 0,
 437                 self.write_register(dc.rd, alu_result)
 438               )
 439
 440         # lui or auipc
 441         i = i.Elif((dc.act & DA.lui_auipc) != 0,
 442                 self.write_register(dc.rd, lui_auipc_result)
 443               )
 444
 445         # jal/jalr
 446         i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
 447                 self.write_register(dc.rd, ft.output_pc + 4)
 448               )
 449
 450         i = i.Elif((dc.act & DA.csr) != 0,
 451                 self.handle_csr(minfo, misa, mstatus, dc, csr)
 452               )
 453
 454         # fence, store, branch
 455         i = i.Elif((dc.act & (DA.fence | DA.fence_i |
 456                               DA.store | DA.branch)) != 0,
 457                 # do nothing
 458               )
 459
 460         return i
 461
 462     def handle_csr(self, minfo, misa, mstatus, dc, csr):
 463         csr_output_value = Signal(32)
 464         csr_written_value = Signal(32)
 465         c = {}
 466
 467         # cycle
 468         c[csr_cycle]  = csr_output_value.eq(minfo.cycle_counter[0:32])
 469         c[csr_cycleh] = csr_output_value.eq(minfo.cycle_counter[32:64])
 470         # time
 471         c[csr_time]  = csr_output_value.eq(minfo.time_counter[0:32])
 472         c[csr_timeh] = csr_output_value.eq(minfo.time_counter[32:64])
 473         # instret
 474         c[csr_instret]  = csr_output_value.eq(minfo.instret_counter[0:32])
 475         c[csr_instreth] = csr_output_value.eq(minfo.instret_counter[32:64])
 476         # mvendorid/march/mimpl/mhart
 477         c[csr_mvendorid] = csr_output_value.eq(minfo.mvendorid)
 478         c[csr_marchid  ] = csr_output_value.eq(minfo.marchid  )
 479         c[csr_mimpid   ] = csr_output_value.eq(minfo.mimpid   )
 480         c[csr_mhartid  ] = csr_output_value.eq(minfo.mhartid  )
 481         # misa
 482         c[csr_misa     ] = csr_output_value.eq(misa.misa)
 483         # mstatus
 484         c[csr_mstatus  ] = [
 485             csr_output_value.eq(mstatus.make()),
 486             csr.evaluate_csr_funct3_op(dc.funct3, csr_written_value,
 487                                                   csr_output_value),
 488             mstatus.mpie.eq(csr_written_value[7]),
 489             mstatus.mie.eq(csr_written_value[3])
 490         ]
 491
 492         return [Case(csr.number, c),
 493                 If(csr.reads,
 494                     self.write_register(dc.rd, csr_output_value)
 495                 )]
 496
 497         """
 498                 `csr_mie: begin
 499                     csr_output_value = 0;
 500                     csr_output_value[11] = mie_meie;
 501                     csr_output_value[9] = mie_seie;
 502                     csr_output_value[8] = mie_ueie;
 503                     csr_output_value[7] = mie_mtie;
 504                     csr_output_value[5] = mie_stie;
 505                     csr_output_value[4] = mie_utie;
 506                     csr_output_value[3] = mie_msie;
 507                     csr_output_value[1] = mie_ssie;
 508                     csr_output_value[0] = mie_usie;
 509                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 510                     if(csr_writes) begin
 511                         mie_meie = csr_written_value[11];
 512                         mie_mtie = csr_written_value[7];
 513                         mie_msie = csr_written_value[3];
 514                     end
 515                 end
 516                 `csr_mtvec: begin
 517                     csr_output_value = mtvec;
 518                 end
 519                 `csr_mscratch: begin
 520                     csr_output_value = mscratch;
 521                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 522                     if(csr_writes)
 523                         mscratch = csr_written_value;
 524                 end
 525                 `csr_mepc: begin
 526                     csr_output_value = mepc;
 527                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 528                     if(csr_writes)
 529                         mepc = csr_written_value;
 530                 end
 531                 `csr_mcause: begin
 532                     csr_output_value = mcause;
 533                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 534                     if(csr_writes)
 535                         mcause = csr_written_value;
 536                 end
 537                 `csr_mip: begin
 538                     csr_output_value = 0;
 539                     csr_output_value[11] = mip_meip;
 540                     csr_output_value[9] = mip_seip;
 541                     csr_output_value[8] = mip_ueip;
 542                     csr_output_value[7] = mip_mtip;
 543                     csr_output_value[5] = mip_stip;
 544                     csr_output_value[4] = mip_utip;
 545                     csr_output_value[3] = mip_msip;
 546                     csr_output_value[1] = mip_ssip;
 547                     csr_output_value[0] = mip_usip;
 548                 end
 549                 endcase
 550                 if(csr_reads)
 551                     write_register(decoder_rd, csr_output_value);
 552             end
 553         end
 554         endcase
 555     end
 556         """
 557     def __init__(self):
 558         self.clk = ClockSignal()
 559         self.reset = ResetSignal()
 560         self.tty_write = Signal()
 561         self.tty_write_data = Signal(8)
 562         self.tty_write_busy = Signal()
 563         self.switch_2 = Signal()
 564         self.switch_3 = Signal()
 565         self.led_1 = Signal()
 566         self.led_3 = Signal()
 567
 568         ram_size = Constant(0x8000)
 569         ram_start = Constant(0x10000, 32)
 570         reset_vector = Signal(32)
 571         mtvec = Signal(32)
 572
 573         reset_vector.eq(ram_start)
 574         mtvec.eq(ram_start + 0x40)
 575
 576         l = []
 577         for i in range(31):
 578             r = Signal(32, name="register%d" % i)
 579             l.append(r)
 580             self.sync += r.eq(Constant(0, 32))
 581         self.registers = Array(l)
 582
 583         mi = MemoryInterface()
 584
 585         mii = Instance("cpu_memory_interface", name="memory_instance",
 586                     p_ram_size = ram_size,
 587                     p_ram_start = ram_start,
 588                     i_clk=ClockSignal(),
 589                     i_rst=ResetSignal(),
 590                     i_fetch_address = mi.fetch_address,
 591                     o_fetch_data = mi.fetch_data,
 592                     o_fetch_valid = mi.fetch_valid,
 593                     i_rw_address = mi.rw_address,
 594                     i_rw_byte_mask = mi.rw_byte_mask,
 595                     i_rw_read_not_write = mi.rw_read_not_write,
 596                     i_rw_active = mi.rw_active,
 597                     i_rw_data_in = mi.rw_data_in,
 598                     o_rw_data_out = mi.rw_data_out,
 599                     o_rw_address_valid = mi.rw_address_valid,
 600                     o_rw_wait = mi.rw_wait,
 601                     o_tty_write = self.tty_write,
 602                     o_tty_write_data = self.tty_write_data,
 603                     i_tty_write_busy = self.tty_write_busy,
 604                     i_switch_2 = self.switch_2,
 605                     i_switch_3 = self.switch_3,
 606                     o_led_1 = self.led_1,
 607                     o_led_3 = self.led_3
 608                   )
 609         self.specials += mii
 610
 611         ft = Fetch(self.comb, self.sync)
 612
 613         fs = Instance("CPUFetchStage", name="fetch_stage",
 614             i_clk=ClockSignal(),
 615             i_rst=ResetSignal(),
 616             o_memory_interface_fetch_address = mi.fetch_address,
 617             i_memory_interface_fetch_data = mi.fetch_data,
 618             i_memory_interface_fetch_valid = mi.fetch_valid,
 619             i_fetch_action = ft.action,
 620             i_target_pc = ft.target_pc,
 621             o_output_pc = ft.output_pc,
 622             o_output_instruction = ft.output_instruction,
 623             o_output_state = ft.output_state,
 624             i_reset_vector = reset_vector,
 625             i_mtvec = mtvec,
 626         )
 627         self.specials += fs
 628
 629         dc = Decoder()
 630
 631         cd = Instance("CPUDecoder", name="decoder",
 632             i_instruction = ft.output_instruction,
 633             o_funct7 = dc.funct7,
 634             o_funct3 = dc.funct3,
 635             o_rd = dc.rd,
 636             o_rs1 = dc.rs1,
 637             o_rs2 = dc.rs2,
 638             o_immediate = dc.immediate,
 639             o_opcode = dc.opcode,
 640             o_decode_action = dc.act
 641         )
 642         self.specials += cd
 643
 644         register_rs1 = Signal(32)
 645         register_rs2 = Signal(32)
 646         self.comb += If(dc.rs1 == 0,
 647                         register_rs1.eq(0)
 648                      ).Else(
 649                         register_rs1.eq(self.registers[dc.rs1-1]))
 650         self.comb += If(dc.rs2 == 0,
 651                         register_rs2.eq(0)
 652                      ).Else(
 653                         register_rs2.eq(self.registers[dc.rs2-1]))
 654
 655         load_store_address = Signal(32)
 656         load_store_address_low_2 = Signal(2)
 657
 658         self.comb += load_store_address.eq(dc.immediate + register_rs1)
 659         self.comb += load_store_address_low_2.eq(
 660                             dc.immediate[:2] + register_rs1[:2])
 661
 662         load_store_misaligned = Signal()
 663
 664         lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3,
 665                                      load_store_address_low_2)
 666         self.comb += lsa
 667
 668         # XXX rwaddr not 31:2 any more
 669         self.comb += mi.rw_address.eq(load_store_address[2:])
 670
 671         unshifted_load_store_byte_mask = Signal(4)
 672
 673         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc))
 674
 675         # XXX yuck.  this will cause migen simulation to fail
 676         # (however conversion to verilog works)
 677         self.comb += mi.rw_byte_mask.eq(
 678                 _Operator("<<", [unshifted_load_store_byte_mask,
 679                                         load_store_address_low_2]))
 680
 681         # XXX not obvious
 682         b3 = Mux(load_store_address_low_2[1],
 683                  Mux(load_store_address_low_2[0], register_rs2[0:8],
 684                                                   register_rs2[8:16]),
 685                  Mux(load_store_address_low_2[0], register_rs2[16:24],
 686                                                   register_rs2[24:32]))
 687         b2 = Mux(load_store_address_low_2[1], register_rs2[0:8],
 688                                               register_rs2[16:24])
 689         b1 = Mux(load_store_address_low_2[0], register_rs2[0:8],
 690                                               register_rs2[8:16])
 691         b0 = register_rs2[0:8]
 692
 693         self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
 694
 695         # XXX not obvious
 696         unmasked_loaded_value = Signal(32)
 697
 698         b0 = Mux(load_store_address_low_2[1],
 699                  Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
 700                                                   mi.rw_data_out[16:24]),
 701                  Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
 702                                                   mi.rw_data_out[0:8]))
 703         b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
 704                                               mi.rw_data_out[8:16])
 705         b23 = mi.rw_data_out[16:32]
 706
 707         self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
 708
 709         # XXX not obvious
 710         loaded_value = Signal(32)
 711
 712         b0 = unmasked_loaded_value[0:8]
 713         b1 = Mux(dc.funct3[0:2] == 0,
 714                 Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8),
 715                 unmasked_loaded_value[8:16])
 716         b2 = Mux(dc.funct3[1] == 0,
 717                 Replicate(~dc.funct3[2] &
 718                            Mux(dc.funct3[0], unmasked_loaded_value[15],
 719                                                   unmasked_loaded_value[7]),
 720                           16),
 721                 unmasked_loaded_value[16:32])
 722
 723         self.comb += loaded_value.eq(Cat(b0, b1, b2))
 724
 725         self.comb += mi.rw_active.eq(~self.reset
 726                         & (ft.output_state == FOS.valid)
 727                         & ~load_store_misaligned
 728                         & ((dc.act & (DA.load | DA.store)) != 0))
 729
 730         self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
 731
 732         # alu
 733         alu_a = Signal(32)
 734         alu_b = Signal(32)
 735         alu_result = Signal(32)
 736
 737         self.comb += alu_a.eq(register_rs1)
 738         self.comb += alu_b.eq(Mux(dc.opcode[5],
 739                                   register_rs2,
 740                                   dc.immediate))
 741
 742         ali = Instance("cpu_alu", name="alu",
 743             i_funct7 = dc.funct7,
 744             i_funct3 = dc.funct3,
 745             i_opcode = dc.opcode,
 746             i_a = alu_a,
 747             i_b = alu_b,
 748             o_result = alu_result
 749         )
 750         self.specials += ali
 751
 752         lui_auipc_result = Signal(32)
 753         self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
 754                                              dc.immediate,
 755                                              dc.immediate + ft.output_pc))
 756
 757         self.comb += ft.target_pc.eq(Cat(0,
 758                     Mux(dc.opcode != OP.jalr,
 759                                 ft.output_pc[1:32],
 760                                 register_rs1[1:32] + dc.immediate[1:32])))
 761
 762         misaligned_jump_target = Signal()
 763         self.comb += misaligned_jump_target.eq(ft.target_pc[1])
 764
 765         branch_arg_a = Signal(32)
 766         branch_arg_b = Signal(32)
 767         self.comb += branch_arg_a.eq(Cat( register_rs1[0:31],
 768                                           register_rs1[31] ^ ~dc.funct3[1]))
 769         self.comb += branch_arg_b.eq(Cat( register_rs2[0:31],
 770                                           register_rs2[31] ^ ~dc.funct3[1]))
 771
 772         branch_taken = Signal()
 773         self.comb += branch_taken.eq(dc.funct3[0] ^
 774                                      Mux(dc.funct3[2],
 775                                          branch_arg_a < branch_arg_b,
 776                                          branch_arg_a == branch_arg_b))
 777
 778         m = M(self.comb, self.sync)
 779         mstatus = MStatus(self.comb, self.sync)
 780         mie = MIE(self.comb, self.sync)
 781         misa = Misa(self.comb, self.sync)
 782         mip = MIP(self.comb, self.sync)
 783
 784         # CSR decoding
 785         csr = CSR(self.comb, self.sync, dc, register_rs1)
 786
 787         self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi,
 788                                  branch_taken, misaligned_jump_target,
 789                                  csr.op_is_valid)
 790
 791         minfo = MInfo(self.comb)
 792
 793         self.sync += If(~self.reset,
 794                         self.main_block(minfo, misa, csr, mi, m,
 795                                         mstatus, ft, dc,
 796                                         load_store_misaligned,
 797                                         loaded_value,
 798                                        alu_result,
 799                                        lui_auipc_result)
 800                      )
 801
 802 if __name__ == "__main__":
 803     example = CPU()
 804     print(verilog.convert(example,
 805          {
 806            example.tty_write,
 807            example.tty_write_data,
 808            example.tty_write_busy,
 809            example.switch_2,
 810            example.switch_3,
 811            example.led_1,
 812            example.led_3,
 813            }))
 814
 815 """
 816
 817     always @(posedge clk) begin:main_block
 818         if(reset) begin
 819             reset_to_initial();
 820             disable main_block;
 821         end
 822         case(fetch_output_state)
 823         `fetch_output_state_empty: begin
 824         end
 825         `fetch_output_state_trap: begin
 826             handle_trap();
 827         end
 828         `fetch_output_state_valid: begin:valid
 829             if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
 830                 handle_trap();
 831             end
 832             else if((decode_action & `decode_action_load) != 0) begin
 833                 if(~memory_interface_rw_wait)
 834                     write_register(decoder_rd, loaded_value);
 835             end
 836             else if((decode_action & `decode_action_op_op_imm) != 0) begin
 837                 write_register(decoder_rd, alu_result);
 838             end
 839             else if((decode_action & `decode_action_lui_auipc) != 0) begin
 840                 write_register(decoder_rd, lui_auipc_result);
 841             end
 842             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 843                 write_register(decoder_rd, fetch_output_pc + 4);
 844             end
 845             else if((decode_action & `decode_action_csr) != 0) begin:csr
 846                 reg [31:0] csr_output_value;
 847                 reg [31:0] csr_written_value;
 848                 csr_output_value = 32'hXXXXXXXX;
 849                 csr_written_value = 32'hXXXXXXXX;
 850                 case(csr_number)
 851                 `csr_cycle: begin
 852                     csr_output_value = cycle_counter[31:0];
 853                 end
 854                 `csr_time: begin
 855                     csr_output_value = time_counter[31:0];
 856                 end
 857                 `csr_instret: begin
 858                     csr_output_value = instret_counter[31:0];
 859                 end
 860                 `csr_cycleh: begin
 861                     csr_output_value = cycle_counter[63:32];
 862                 end
 863                 `csr_timeh: begin
 864                     csr_output_value = time_counter[63:32];
 865                 end
 866                 `csr_instreth: begin
 867                     csr_output_value = instret_counter[63:32];
 868                 end
 869                 `csr_mvendorid: begin
 870                     csr_output_value = mvendorid;
 871                 end
 872                 `csr_marchid: begin
 873                     csr_output_value = marchid;
 874                 end
 875                 `csr_mimpid: begin
 876                     csr_output_value = mimpid;
 877                 end
 878                 `csr_mhartid: begin
 879                     csr_output_value = mhartid;
 880                 end
 881                 `csr_misa: begin
 882                     csr_output_value = misa;
 883                 end
 884                 `csr_mstatus: begin
 885                     csr_output_value = make_mstatus(mstatus_tsr,
 886                                                     mstatus_tw,
 887                                                     mstatus_tvm,
 888                                                     mstatus_mxr,
 889                                                     mstatus_sum,
 890                                                     mstatus_mprv,
 891                                                     mstatus_xs,
 892                                                     mstatus_fs,
 893                                                     mstatus_mpp,
 894                                                     mstatus_spp,
 895                                                     mstatus_mpie,
 896                                                     mstatus_spie,
 897                                                     mstatus_upie,
 898                                                     mstatus_mie,
 899                                                     mstatus_sie,
 900                                                     mstatus_uie);
 901                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 902                     if(csr_writes) begin
 903                         mstatus_mpie = csr_written_value[7];
 904                         mstatus_mie = csr_written_value[3];
 905                     end
 906                 end
 907                 `csr_mie: begin
 908                     csr_output_value = 0;
 909                     csr_output_value[11] = mie_meie;
 910                     csr_output_value[9] = mie_seie;
 911                     csr_output_value[8] = mie_ueie;
 912                     csr_output_value[7] = mie_mtie;
 913                     csr_output_value[5] = mie_stie;
 914                     csr_output_value[4] = mie_utie;
 915                     csr_output_value[3] = mie_msie;
 916                     csr_output_value[1] = mie_ssie;
 917                     csr_output_value[0] = mie_usie;
 918                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 919                     if(csr_writes) begin
 920                         mie_meie = csr_written_value[11];
 921                         mie_mtie = csr_written_value[7];
 922                         mie_msie = csr_written_value[3];
 923                     end
 924                 end
 925                 `csr_mtvec: begin
 926                     csr_output_value = mtvec;
 927                 end
 928                 `csr_mscratch: begin
 929                     csr_output_value = mscratch;
 930                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 931                     if(csr_writes)
 932                         mscratch = csr_written_value;
 933                 end
 934                 `csr_mepc: begin
 935                     csr_output_value = mepc;
 936                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 937                     if(csr_writes)
 938                         mepc = csr_written_value;
 939                 end
 940                 `csr_mcause: begin
 941                     csr_output_value = mcause;
 942                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 943                     if(csr_writes)
 944                         mcause = csr_written_value;
 945                 end
 946                 `csr_mip: begin
 947                     csr_output_value = 0;
 948                     csr_output_value[11] = mip_meip;
 949                     csr_output_value[9] = mip_seip;
 950                     csr_output_value[8] = mip_ueip;
 951                     csr_output_value[7] = mip_mtip;
 952                     csr_output_value[5] = mip_stip;
 953                     csr_output_value[4] = mip_utip;
 954                     csr_output_value[3] = mip_msip;
 955                     csr_output_value[1] = mip_ssip;
 956                     csr_output_value[0] = mip_usip;
 957                 end
 958                 endcase
 959                 if(csr_reads)
 960                     write_register(decoder_rd, csr_output_value);
 961             end
 962             else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
 963                 // do nothing
 964             end
 965         end
 966         endcase
 967     end
 968
 969 endmodule
 970 """
 971