cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 import string
  30 from migen import *
  31 from migen.fhdl import verilog
  32 from migen.fhdl.structure import _Operator
  33
  34 from riscvdefs import *
  35 from cpudefs import *
  36
  37 class MemoryInterface:
  38     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  39     fetch_data = Signal(32, name="memory_interface_fetch_data")
  40     fetch_valid = Signal(name="memory_interface_fetch_valid")
  41     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  42     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  43     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  44     rw_active = Signal(name="memory_interface_rw_active")
  45     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  46     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  47     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  48     rw_wait = Signal(name="memory_interface_rw_wait")
  49
  50
  51 class Decoder:
  52     funct7 = Signal(7, name="decoder_funct7")
  53     funct3 = Signal(3, name="decoder_funct3")
  54     rd = Signal(5, name="decoder_rd")
  55     rs1 = Signal(5, name="decoder_rs1")
  56     rs2 = Signal(5, name="decoder_rs2")
  57     immediate = Signal(32, name="decoder_immediate")
  58     opcode = Signal(7, name="decoder_opcode")
  59     act = Signal(decode_action, name="decoder_action")
  60
  61 class MStatus:
  62     def __init__(self, comb, sync):
  63         self.comb = comb
  64         self.sync = sync
  65         self.mpie = Signal(name="mstatus_mpie")
  66         self.mie = Signal(name="mstatus_mie")
  67         self.mprv = Signal(name="mstatus_mprv")
  68         self.tsr = Signal(name="mstatus_tsr")
  69         self.tw = Signal(name="mstatus_tw")
  70         self.tvm = Signal(name="mstatus_tvm")
  71         self.mxr = Signal(name="mstatus_mxr")
  72         self._sum = Signal(name="mstatus_sum")
  73         self.xs = Signal(name="mstatus_xs")
  74         self.fs = Signal(name="mstatus_fs")
  75         self.mpp = Signal(2, name="mstatus_mpp")
  76         self.spp = Signal(name="mstatus_spp")
  77         self.spie = Signal(name="mstatus_spie")
  78         self.upie = Signal(name="mstatus_upie")
  79         self.sie = Signal(name="mstatus_sie")
  80         self.uie = Signal(name="mstatus_uie")
  81
  82         for n in dir(self):
  83             if n in ['make', 'mpp', 'comb', 'sync'] or n.startswith("_"):
  84                 continue
  85             self.comb += getattr(self, n).eq(0x0)
  86         self.comb += self.mpp.eq(0b11)
  87
  88         self.sync += self.mie.eq(0)
  89         self.sync += self.mpie.eq(0)
  90
  91     def make(self):
  92         return Cat(
  93                 self.uie, self.sie, Constant(0), self.mie,
  94                 self.upie, self.spie, Constant(0), self.mpie,
  95                 self.spp, Constant(0, 2), self.mpp,
  96                 self.fs, self.xs, self.mprv, self._sum,
  97                 self.mxr, self.tvm, self.tw, self.tsr,
  98                 Constant(0, 8),
  99                 (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2))
 100                 )
 101
 102
 103 class MIE:
 104     def __init__(self, comb, sync):
 105         self.comb = comb
 106         self.sync = sync
 107         self.meie = Signal(name="mie_meie")
 108         self.mtie = Signal(name="mie_mtie")
 109         self.msie = Signal(name="mie_msie")
 110         self.ueie = Signal(name="mie_ueie")
 111         self.stie = Signal(name="mie_stie")
 112         self.utie = Signal(name="mie_utie")
 113         self.ssie = Signal(name="mie_ssie")
 114         self.usie = Signal(name="mie_usie")
 115
 116         for n in dir(self):
 117             if n in ['make', 'comb', 'sync'] or n.startswith("_"):
 118                 continue
 119             self.comb += getattr(self, n).eq(0x0)
 120
 121         self.sync += self.meie.eq(0)
 122         self.sync += self.mtie.eq(0)
 123         self.sync += self.msie.eq(0)
 124
 125 class MIP:
 126     def __init__(self, comb, sync):
 127         self.comb = comb
 128         self.sync = sync
 129         self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts
 130         self.seip = Signal(name="mip_seip")
 131         self.ueip = Signal(name="mip_uiep")
 132         self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts
 133         self.stip = Signal(name="mip_stip")
 134         self.msip = Signal(name="mip_stip")
 135         self.utip = Signal(name="mip_utip")
 136         self.ssip = Signal(name="mip_ssip")
 137         self.usip = Signal(name="mip_usip")
 138
 139         for n in dir(self):
 140             if n in ['comb', 'sync'] or n.startswith("_"):
 141                 continue
 142             self.comb += getattr(self, n).eq(0x0)
 143
 144
 145 class M:
 146     def __init__(self, comb, sync):
 147         self.comb = comb
 148         self.sync = sync
 149         self.mcause = Signal(32)
 150         self.mepc = Signal(32)
 151         self.mscratch = Signal(32)
 152         self.sync += self.mcause.eq(0)
 153         self.sync += self.mepc.eq(0) # 32'hXXXXXXXX;
 154         self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
 155
 156
 157 class Misa:
 158     def __init__(self, comb, sync):
 159         self.comb = comb
 160         self.sync = sync
 161         self.misa = Signal(32)
 162         cl = []
 163         for l in list(string.ascii_lowercase):
 164             value = 1 if l == 'i' else 0
 165             cl.append(Constant(value))
 166         cl.append(Constant(0, 4))
 167         cl.append(Constant(0b01, 2))
 168         self.comb += self.misa.eq(Cat(cl))
 169
 170
 171 class Fetch:
 172     def __init__(self, comb, sync):
 173         self.comb = comb
 174         self.sync = sync
 175         self.action = Signal(fetch_action, name="fetch_action")
 176         self.target_pc = Signal(32, name="fetch_target_pc")
 177         self.output_pc = Signal(32, name="fetch_output_pc")
 178         self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
 179         self.output_state = Signal(fetch_output_state,name="fetch_output_state")
 180
 181     def get_fetch_action(self, dc, load_store_misaligned, mi,
 182                          branch_taken, misaligned_jump_target,
 183                          csr_op_is_valid):
 184         c = {}
 185         c["default"] = self.action.eq(FA.default) # XXX should be 32'XXXXXXXX?
 186         c[FOS.empty] = self.action.eq(FA.default)
 187         c[FOS.trap] = self.action.eq(FA.ack_trap)
 188
 189         # illegal instruction -> error trap
 190         i= If((dc.act & DA.trap_illegal_instruction) != 0,
 191                  self.action.eq(FA.error_trap)
 192               )
 193
 194         # ecall / ebreak -> noerror trap
 195         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
 196                  self.action.eq(FA.noerror_trap))
 197
 198         # load/store: check alignment, check wait
 199         i = i.Elif((dc.act & (DA.load | DA.store)) != 0,
 200                 If((load_store_misaligned | ~mi.rw_address_valid),
 201                     self.action.eq(FA.error_trap) # misaligned or invalid addr
 202                 ).Elif(mi.rw_wait,
 203                     self.action.eq(FA.wait) # wait
 204                 ).Else(
 205                     self.action.eq(FA.default) # ok
 206                 )
 207               )
 208
 209         # fence
 210         i = i.Elif((dc.act & DA.fence) != 0,
 211                  self.action.eq(FA.fence))
 212
 213         # branch -> misaligned=error, otherwise jump
 214         i = i.Elif((dc.act & DA.branch) != 0,
 215                 If(misaligned_jump_target,
 216                     self.action.eq(FA.error_trap)
 217                 ).Else(
 218                     self.action.eq(FA.jump)
 219                 )
 220               )
 221
 222         # jal/jalr -> misaligned=error, otherwise jump
 223         i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
 224                 If(misaligned_jump_target,
 225                     self.action.eq(FA.error_trap)
 226                 ).Else(
 227                     self.action.eq(FA.jump)
 228                 )
 229               )
 230
 231         # csr -> opvalid=ok, else error trap
 232         i = i.Elif((dc.act & DA.csr) != 0,
 233                 If(csr_op_is_valid,
 234                     self.action.eq(FA.default)
 235                 ).Else(
 236                     self.action.eq(FA.error_trap)
 237                 )
 238               )
 239
 240         c[FOS.valid] = i
 241
 242         return Case(self.output_state, c)
 243
 244
 245 class CPU(Module):
 246     """
 247     """
 248
 249     def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
 250         """ returns whether a load/store is misaligned
 251         """
 252         return Case(funct3[:2],
 253                 { F3.sb: ls.eq(Constant(0)),
 254                   F3.sh: ls.eq(load_store_address_low_2[0] != 0),
 255                   F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
 256                   "default": ls.eq(Constant(1))
 257                 })
 258
 259     def get_lsbm(self, dc):
 260         return Cat(Constant(1),
 261                    Mux((dc.funct3[1] | dc.funct3[0]),
 262                        Constant(1), Constant(0)),
 263                    Mux((dc.funct3[1]),
 264                        Constant(0b11, 2), Constant(0, 2)))
 265
 266     # XXX this happens to get done by various self.sync actions
 267     #def reset_to_initial(self, m, mstatus, mie, registers):
 268     #    return [m.mcause.eq(0),
 269     #            ]
 270
 271     def write_register(self, register_number, value):
 272         return If(register_number != 0,
 273                   self.registers[register_number].eq(value)
 274                )
 275
 276     def evaluate_csr_funct3_op(self, funct3, previous_value, written_value):
 277         c = { "default": Constant(0, 32)}
 278         for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value
 279         for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value
 280         for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
 281         return Case(funct3, c)
 282
 283     def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
 284         s = [ms.mpie.eq(ms.mie),
 285              ms.mie.eq(0),
 286              m.mepc.eq(Mux(ft.action == FA.noerror_trap,
 287                            ft.output_pc + 4,
 288                            ft.output_pc))]
 289
 290         # fetch action ack trap
 291         i = If(ft.action == FA.ack_trap,
 292                 m.mcause.eq(cause_instruction_access_fault)
 293               )
 294
 295         # ecall/ebreak
 296         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
 297                 m.mcause.eq(Mux(dc.immediate[0],
 298                                 cause_machine_environment_call,
 299                                 cause_breakpoint))
 300               )
 301
 302         # load
 303         i = i.Elif((dc.act & DA.load) != 0,
 304                 If(load_store_misaligned,
 305                     m.mcause.eq(cause_load_address_misaligned)
 306                 ).Else(
 307                     m.mcause.eq(cause_load_access_fault)
 308                 )
 309               )
 310
 311         # store
 312         i = i.Elif((dc.act & DA.store) != 0,
 313                 If(load_store_misaligned,
 314                     m.mcause.eq(cause_store_amo_address_misaligned)
 315                 ).Else(
 316                     m.mcause.eq(cause_store_amo_access_fault)
 317                 )
 318               )
 319
 320         # jal/jalr -> misaligned=error, otherwise jump
 321         i = i.Elif((dc.act & (DA.jal | DA.jalr | DA.branch)) != 0,
 322                 m.mcause.eq(cause_instruction_address_misaligned)
 323               )
 324
 325         # defaults to illegal instruction
 326         i = i.Else(m.mcause.eq(cause_illegal_instruction))
 327
 328         s.append(i)
 329         return s
 330
 331     def get_csr_op_is_valid(self, csr_op_is_valid, csr_number,
 332                                   csr_reads, csr_writes):
 333         """ determines if a CSR is valid
 334         """
 335         c = {}
 336         # invalid csrs
 337         for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr,
 338                   csr_uie, csr_utvec, csr_uscratch, csr_uepc,
 339                   csr_ucause, csr_utval, csr_uip, csr_sstatus,
 340                   csr_sedeleg, csr_sideleg, csr_sie, csr_stvec,
 341                   csr_scounteren, csr_sscratch, csr_sepc, csr_scause,
 342                   csr_stval, csr_sip, csr_satp, csr_medeleg,
 343                   csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]:
 344             c[f] = csr_op_is_valid.eq(0)
 345
 346         # not-writeable -> ok
 347         for f in [csr_cycle, csr_time, csr_instret, csr_cycleh,
 348                   csr_timeh, csr_instreth, csr_mvendorid, csr_marchid,
 349                   csr_mimpid, csr_mhartid]:
 350             c[f] = csr_op_is_valid.eq(~csr_writes)
 351
 352         # valid csrs
 353         for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec,
 354                   csr_mscratch, csr_mepc, csr_mcause, csr_mip]:
 355             c[f] = csr_op_is_valid.eq(1)
 356
 357         # not implemented / default
 358         for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret,
 359                   csr_mcycleh, csr_minstreth, "default"]:
 360             c[f] = csr_op_is_valid.eq(0)
 361
 362         return Case(csr_number, c)
 363
 364     def __init__(self):
 365         self.clk = ClockSignal()
 366         self.reset = ResetSignal()
 367         self.tty_write = Signal()
 368         self.tty_write_data = Signal(8)
 369         self.tty_write_busy = Signal()
 370         self.switch_2 = Signal()
 371         self.switch_3 = Signal()
 372         self.led_1 = Signal()
 373         self.led_3 = Signal()
 374
 375         ram_size = Constant(0x8000)
 376         ram_start = Constant(0x10000, 32)
 377         reset_vector = Signal(32)
 378         mtvec = Signal(32)
 379
 380         reset_vector.eq(ram_start)
 381         mtvec.eq(ram_start + 0x40)
 382
 383         l = []
 384         for i in range(31):
 385             r = Signal(32, name="register%d" % i)
 386             l.append(r)
 387             self.sync += r.eq(Constant(0, 32))
 388         self.registers = Array(l)
 389
 390         mi = MemoryInterface()
 391
 392         mii = Instance("cpu_memory_interface", name="memory_instance",
 393                     p_ram_size = ram_size,
 394                     p_ram_start = ram_start,
 395                     i_clk=ClockSignal(),
 396                     i_rst=ResetSignal(),
 397                     i_fetch_address = mi.fetch_address,
 398                     o_fetch_data = mi.fetch_data,
 399                     o_fetch_valid = mi.fetch_valid,
 400                     i_rw_address = mi.rw_address,
 401                     i_rw_byte_mask = mi.rw_byte_mask,
 402                     i_rw_read_not_write = mi.rw_read_not_write,
 403                     i_rw_active = mi.rw_active,
 404                     i_rw_data_in = mi.rw_data_in,
 405                     o_rw_data_out = mi.rw_data_out,
 406                     o_rw_address_valid = mi.rw_address_valid,
 407                     o_rw_wait = mi.rw_wait,
 408                     o_tty_write = self.tty_write,
 409                     o_tty_write_data = self.tty_write_data,
 410                     i_tty_write_busy = self.tty_write_busy,
 411                     i_switch_2 = self.switch_2,
 412                     i_switch_3 = self.switch_3,
 413                     o_led_1 = self.led_1,
 414                     o_led_3 = self.led_3
 415                   )
 416         self.specials += mii
 417
 418         ft = Fetch(self.comb, self.sync)
 419
 420         fs = Instance("CPUFetchStage", name="fetch_stage",
 421             i_clk=ClockSignal(),
 422             i_rst=ResetSignal(),
 423             o_memory_interface_fetch_address = mi.fetch_address,
 424             i_memory_interface_fetch_data = mi.fetch_data,
 425             i_memory_interface_fetch_valid = mi.fetch_valid,
 426             i_fetch_action = ft.action,
 427             i_target_pc = ft.target_pc,
 428             o_output_pc = ft.output_pc,
 429             o_output_instruction = ft.output_instruction,
 430             o_output_state = ft.output_state,
 431             i_reset_vector = reset_vector,
 432             i_mtvec = mtvec,
 433         )
 434         self.specials += fs
 435
 436         dc = Decoder()
 437
 438         cd = Instance("CPUDecoder", name="decoder",
 439             i_instruction = ft.output_instruction,
 440             o_funct7 = dc.funct7,
 441             o_funct3 = dc.funct3,
 442             o_rd = dc.rd,
 443             o_rs1 = dc.rs1,
 444             o_rs2 = dc.rs2,
 445             o_immediate = dc.immediate,
 446             o_opcode = dc.opcode,
 447             o_decode_action = dc.act
 448         )
 449         self.specials += cd
 450
 451         register_rs1 = Signal(32)
 452         register_rs2 = Signal(32)
 453         self.comb += If(dc.rs1 == 0,
 454                         register_rs1.eq(0)
 455                      ).Else(
 456                         register_rs1.eq(self.registers[dc.rs1-1]))
 457         self.comb += If(dc.rs2 == 0,
 458                         register_rs2.eq(0)
 459                      ).Else(
 460                         register_rs2.eq(self.registers[dc.rs2-1]))
 461
 462         load_store_address = Signal(32)
 463         load_store_address_low_2 = Signal(2)
 464
 465         self.comb += load_store_address.eq(dc.immediate + register_rs1)
 466         self.comb += load_store_address_low_2.eq(
 467                             dc.immediate[:2] + register_rs1[:2])
 468
 469         load_store_misaligned = Signal()
 470
 471         lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3,
 472                                      load_store_address_low_2)
 473         self.comb += lsa
 474
 475         # XXX rwaddr not 31:2 any more
 476         self.comb += mi.rw_address.eq(load_store_address[2:])
 477
 478         unshifted_load_store_byte_mask = Signal(4)
 479
 480         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc))
 481
 482         # XXX yuck.  this will cause migen simulation to fail
 483         # (however conversion to verilog works)
 484         self.comb += mi.rw_byte_mask.eq(
 485                 _Operator("<<", [unshifted_load_store_byte_mask,
 486                                         load_store_address_low_2]))
 487
 488         # XXX not obvious
 489         b3 = Mux(load_store_address_low_2[1],
 490                  Mux(load_store_address_low_2[0], register_rs2[0:8],
 491                                                   register_rs2[8:16]),
 492                  Mux(load_store_address_low_2[0], register_rs2[16:24],
 493                                                   register_rs2[24:32]))
 494         b2 = Mux(load_store_address_low_2[1], register_rs2[0:8],
 495                                               register_rs2[16:24])
 496         b1 = Mux(load_store_address_low_2[0], register_rs2[0:8],
 497                                               register_rs2[8:16])
 498         b0 = register_rs2[0:8]
 499
 500         self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
 501
 502         # XXX not obvious
 503         unmasked_loaded_value = Signal(32)
 504
 505         b0 = Mux(load_store_address_low_2[1],
 506                  Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
 507                                                   mi.rw_data_out[16:24]),
 508                  Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
 509                                                   mi.rw_data_out[0:8]))
 510         b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
 511                                               mi.rw_data_out[8:16])
 512         b23 = mi.rw_data_out[16:32]
 513
 514         self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
 515
 516         # XXX not obvious
 517         loaded_value = Signal(32)
 518
 519         b0 = unmasked_loaded_value[0:8]
 520         b1 = Mux(dc.funct3[0:2] == 0,
 521                 Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8),
 522                 unmasked_loaded_value[8:16])
 523         b2 = Mux(dc.funct3[1] == 0,
 524                 Replicate(~dc.funct3[2] &
 525                            Mux(dc.funct3[0], unmasked_loaded_value[15],
 526                                                   unmasked_loaded_value[7]),
 527                           16),
 528                 unmasked_loaded_value[16:32])
 529
 530         self.comb += loaded_value.eq(Cat(b0, b1, b2))
 531
 532         self.comb += mi.rw_active.eq(~self.reset
 533                         & (ft.output_state == FOS.valid)
 534                         & ~load_store_misaligned
 535                         & ((dc.act & (DA.load | DA.store)) != 0))
 536
 537         self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
 538
 539         # alu
 540         alu_a = Signal(32)
 541         alu_b = Signal(32)
 542         alu_result = Signal(32)
 543
 544         self.comb += alu_a.eq(register_rs1)
 545         self.comb += alu_b.eq(Mux(dc.opcode[5],
 546                                   register_rs2,
 547                                   dc.immediate))
 548
 549         ali = Instance("cpu_alu", name="alu",
 550             i_funct7 = dc.funct7,
 551             i_funct3 = dc.funct3,
 552             i_opcode = dc.opcode,
 553             i_a = alu_a,
 554             i_b = alu_b,
 555             o_result = alu_result
 556         )
 557         self.specials += ali
 558
 559         lui_auipc_result = Signal(32)
 560         self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
 561                                              dc.immediate,
 562                                              dc.immediate + ft.output_pc))
 563
 564         self.comb += ft.target_pc.eq(Cat(0,
 565                     Mux(dc.opcode != OP.jalr,
 566                                 ft.output_pc[1:32],
 567                                 register_rs1[1:32] + dc.immediate[1:32])))
 568
 569         misaligned_jump_target = Signal()
 570         self.comb += misaligned_jump_target.eq(ft.target_pc[1])
 571
 572         branch_arg_a = Signal(32)
 573         branch_arg_b = Signal(32)
 574         self.comb += branch_arg_a.eq(Cat( register_rs1[0:31],
 575                                           register_rs1[31] ^ ~dc.funct3[1]))
 576         self.comb += branch_arg_b.eq(Cat( register_rs2[0:31],
 577                                           register_rs2[31] ^ ~dc.funct3[1]))
 578
 579         branch_taken = Signal()
 580         self.comb += branch_taken.eq(dc.funct3[0] ^
 581                                      Mux(dc.funct3[2],
 582                                          branch_arg_a < branch_arg_b,
 583                                          branch_arg_a == branch_arg_b))
 584
 585         m = M(self.comb, self.sync)
 586         mstatus = MStatus(self.comb, self.sync)
 587         mie = MIE(self.comb, self.sync)
 588
 589         misa = Misa(self.comb, self.sync)
 590
 591         mvendorid = Signal(32)
 592         marchid = Signal(32)
 593         mimpid = Signal(32)
 594         mhartid = Signal(32)
 595         self.comb += mvendorid.eq(Constant(0, 32))
 596         self.comb += marchid.eq(Constant(0, 32))
 597         self.comb += mimpid.eq(Constant(0, 32))
 598         self.comb += mhartid.eq(Constant(0, 32))
 599
 600         mip = MIP(self.comb, self.sync)
 601
 602         csr_op_is_valid = Signal()
 603
 604         self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi,
 605                                  branch_taken, misaligned_jump_target,
 606                                  csr_op_is_valid)
 607
 608         #self.comb += self.handle_trap(m, mstatus, ft, dc, load_store_misaligned)
 609         # CSR decoding
 610         csr_number = Signal(12)
 611         csr_input_value = Signal(32)
 612         csr_reads = Signal()
 613         csr_writes = Signal()
 614
 615         self.comb += csr_number.eq(dc.immediate)
 616         self.comb += csr_input_value.eq(Mux(dc.funct3[2],
 617                                             dc.rs1,
 618                                             register_rs1))
 619         self.comb += csr_reads.eq(dc.funct3[1] | (dc.rd != 0))
 620         self.comb += csr_writes.eq(~dc.funct3[1] | (dc.rs1 != 0))
 621
 622         self.comb += self.get_csr_op_is_valid(csr_op_is_valid, csr_number,
 623                                               csr_reads, csr_writes)
 624
 625 if __name__ == "__main__":
 626     example = CPU()
 627     print(verilog.convert(example,
 628          {
 629            example.tty_write,
 630            example.tty_write_data,
 631            example.tty_write_busy,
 632            example.switch_2,
 633            example.switch_3,
 634            example.led_1,
 635            example.led_3,
 636            }))
 637
 638 """
 639
 640     wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter
 641     wire [63:0] time_counter = 0; // TODO: implement time_counter
 642     wire [63:0] instret_counter = 0; // TODO: implement instret_counter
 643
 644     always @(posedge clk) begin:main_block
 645         if(reset) begin
 646             reset_to_initial();
 647             disable main_block;
 648         end
 649         case(fetch_output_state)
 650         `fetch_output_state_empty: begin
 651         end
 652         `fetch_output_state_trap: begin
 653             handle_trap();
 654         end
 655         `fetch_output_state_valid: begin:valid
 656             if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
 657                 handle_trap();
 658             end
 659             else if((decode_action & `decode_action_load) != 0) begin
 660                 if(~memory_interface_rw_wait)
 661                     write_register(decoder_rd, loaded_value);
 662             end
 663             else if((decode_action & `decode_action_op_op_imm) != 0) begin
 664                 write_register(decoder_rd, alu_result);
 665             end
 666             else if((decode_action & `decode_action_lui_auipc) != 0) begin
 667                 write_register(decoder_rd, lui_auipc_result);
 668             end
 669             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 670                 write_register(decoder_rd, fetch_output_pc + 4);
 671             end
 672             else if((decode_action & `decode_action_csr) != 0) begin:csr
 673                 reg [31:0] csr_output_value;
 674                 reg [31:0] csr_written_value;
 675                 csr_output_value = 32'hXXXXXXXX;
 676                 csr_written_value = 32'hXXXXXXXX;
 677                 case(csr_number)
 678                 `csr_cycle: begin
 679                     csr_output_value = cycle_counter[31:0];
 680                 end
 681                 `csr_time: begin
 682                     csr_output_value = time_counter[31:0];
 683                 end
 684                 `csr_instret: begin
 685                     csr_output_value = instret_counter[31:0];
 686                 end
 687                 `csr_cycleh: begin
 688                     csr_output_value = cycle_counter[63:32];
 689                 end
 690                 `csr_timeh: begin
 691                     csr_output_value = time_counter[63:32];
 692                 end
 693                 `csr_instreth: begin
 694                     csr_output_value = instret_counter[63:32];
 695                 end
 696                 `csr_mvendorid: begin
 697                     csr_output_value = mvendorid;
 698                 end
 699                 `csr_marchid: begin
 700                     csr_output_value = marchid;
 701                 end
 702                 `csr_mimpid: begin
 703                     csr_output_value = mimpid;
 704                 end
 705                 `csr_mhartid: begin
 706                     csr_output_value = mhartid;
 707                 end
 708                 `csr_misa: begin
 709                     csr_output_value = misa;
 710                 end
 711                 `csr_mstatus: begin
 712                     csr_output_value = make_mstatus(mstatus_tsr,
 713                                                     mstatus_tw,
 714                                                     mstatus_tvm,
 715                                                     mstatus_mxr,
 716                                                     mstatus_sum,
 717                                                     mstatus_mprv,
 718                                                     mstatus_xs,
 719                                                     mstatus_fs,
 720                                                     mstatus_mpp,
 721                                                     mstatus_spp,
 722                                                     mstatus_mpie,
 723                                                     mstatus_spie,
 724                                                     mstatus_upie,
 725                                                     mstatus_mie,
 726                                                     mstatus_sie,
 727                                                     mstatus_uie);
 728                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 729                     if(csr_writes) begin
 730                         mstatus_mpie = csr_written_value[7];
 731                         mstatus_mie = csr_written_value[3];
 732                     end
 733                 end
 734                 `csr_mie: begin
 735                     csr_output_value = 0;
 736                     csr_output_value[11] = mie_meie;
 737                     csr_output_value[9] = mie_seie;
 738                     csr_output_value[8] = mie_ueie;
 739                     csr_output_value[7] = mie_mtie;
 740                     csr_output_value[5] = mie_stie;
 741                     csr_output_value[4] = mie_utie;
 742                     csr_output_value[3] = mie_msie;
 743                     csr_output_value[1] = mie_ssie;
 744                     csr_output_value[0] = mie_usie;
 745                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 746                     if(csr_writes) begin
 747                         mie_meie = csr_written_value[11];
 748                         mie_mtie = csr_written_value[7];
 749                         mie_msie = csr_written_value[3];
 750                     end
 751                 end
 752                 `csr_mtvec: begin
 753                     csr_output_value = mtvec;
 754                 end
 755                 `csr_mscratch: begin
 756                     csr_output_value = mscratch;
 757                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 758                     if(csr_writes)
 759                         mscratch = csr_written_value;
 760                 end
 761                 `csr_mepc: begin
 762                     csr_output_value = mepc;
 763                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 764                     if(csr_writes)
 765                         mepc = csr_written_value;
 766                 end
 767                 `csr_mcause: begin
 768                     csr_output_value = mcause;
 769                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 770                     if(csr_writes)
 771                         mcause = csr_written_value;
 772                 end
 773                 `csr_mip: begin
 774                     csr_output_value = 0;
 775                     csr_output_value[11] = mip_meip;
 776                     csr_output_value[9] = mip_seip;
 777                     csr_output_value[8] = mip_ueip;
 778                     csr_output_value[7] = mip_mtip;
 779                     csr_output_value[5] = mip_stip;
 780                     csr_output_value[4] = mip_utip;
 781                     csr_output_value[3] = mip_msip;
 782                     csr_output_value[1] = mip_ssip;
 783                     csr_output_value[0] = mip_usip;
 784                 end
 785                 endcase
 786                 if(csr_reads)
 787                     write_register(decoder_rd, csr_output_value);
 788             end
 789             else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
 790                 // do nothing
 791             end
 792         end
 793         endcase
 794     end
 795
 796 endmodule
 797 """
 798