cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 import string
  30 from migen import *
  31 from migen.fhdl import verilog
  32 from migen.fhdl.structure import _Operator
  33
  34 from riscvdefs import *
  35 from cpudefs import *
  36
  37 class MemoryInterface:
  38     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  39     fetch_data = Signal(32, name="memory_interface_fetch_data")
  40     fetch_valid = Signal(name="memory_interface_fetch_valid")
  41     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  42     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  43     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  44     rw_active = Signal(name="memory_interface_rw_active")
  45     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  46     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  47     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  48     rw_wait = Signal(name="memory_interface_rw_wait")
  49
  50
  51 class Decoder:
  52     funct7 = Signal(7, name="decoder_funct7")
  53     funct3 = Signal(3, name="decoder_funct3")
  54     rd = Signal(5, name="decoder_rd")
  55     rs1 = Signal(5, name="decoder_rs1")
  56     rs2 = Signal(5, name="decoder_rs2")
  57     immediate = Signal(32, name="decoder_immediate")
  58     opcode = Signal(7, name="decoder_opcode")
  59     act = Signal(decode_action, name="decoder_action")
  60
  61 class MStatus:
  62     def __init__(self, comb, sync):
  63         self.comb = comb
  64         self.sync = sync
  65         self.mpie = Signal(name="mstatus_mpie")
  66         self.mie = Signal(name="mstatus_mie")
  67         self.mprv = Signal(name="mstatus_mprv")
  68         self.tsr = Signal(name="mstatus_tsr")
  69         self.tw = Signal(name="mstatus_tw")
  70         self.tvm = Signal(name="mstatus_tvm")
  71         self.mxr = Signal(name="mstatus_mxr")
  72         self._sum = Signal(name="mstatus_sum")
  73         self.xs = Signal(name="mstatus_xs")
  74         self.fs = Signal(name="mstatus_fs")
  75         self.mpp = Signal(2, name="mstatus_mpp")
  76         self.spp = Signal(name="mstatus_spp")
  77         self.spie = Signal(name="mstatus_spie")
  78         self.upie = Signal(name="mstatus_upie")
  79         self.sie = Signal(name="mstatus_sie")
  80         self.uie = Signal(name="mstatus_uie")
  81
  82         for n in dir(self):
  83             if n in ['make', 'mpp', 'comb', 'sync'] or n.startswith("_"):
  84                 continue
  85             self.comb += getattr(self, n).eq(0x0)
  86         self.comb += self.mpp.eq(0b11)
  87
  88         self.sync += self.mie.eq(0)
  89         self.sync += self.mpie.eq(0)
  90
  91     def make(self):
  92         return Cat(
  93                 self.uie, self.sie, Constant(0), self.mie,
  94                 self.upie, self.spie, Constant(0), self.mpie,
  95                 self.spp, Constant(0, 2), self.mpp,
  96                 self.fs, self.xs, self.mprv, self._sum,
  97                 self.mxr, self.tvm, self.tw, self.tsr,
  98                 Constant(0, 8),
  99                 (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2))
 100                 )
 101
 102
 103 class MIE:
 104     def __init__(self, comb, sync):
 105         self.comb = comb
 106         self.sync = sync
 107         self.meie = Signal(name="mie_meie")
 108         self.mtie = Signal(name="mie_mtie")
 109         self.msie = Signal(name="mie_msie")
 110         self.seie = Signal(name="mie_seie")
 111         self.ueie = Signal(name="mie_ueie")
 112         self.stie = Signal(name="mie_stie")
 113         self.utie = Signal(name="mie_utie")
 114         self.ssie = Signal(name="mie_ssie")
 115         self.usie = Signal(name="mie_usie")
 116
 117         for n in dir(self):
 118             if n in ['make', 'comb', 'sync'] or n.startswith("_"):
 119                 continue
 120             self.comb += getattr(self, n).eq(0x0)
 121
 122         self.sync += self.meie.eq(0)
 123         self.sync += self.mtie.eq(0)
 124         self.sync += self.msie.eq(0)
 125
 126     def make(self):
 127         return Cat( self.usie, self.ssie, 0, self.msie,
 128                     self.utie, self.stie, 0, self.mtie,
 129                     self.ueie, self.seie, 0, self.meie, )
 130
 131
 132 class MIP:
 133     def __init__(self, comb, sync):
 134         self.comb = comb
 135         self.sync = sync
 136         self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts
 137         self.seip = Signal(name="mip_seip")
 138         self.ueip = Signal(name="mip_uiep")
 139         self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts
 140         self.stip = Signal(name="mip_stip")
 141         self.msip = Signal(name="mip_stip")
 142         self.utip = Signal(name="mip_utip")
 143         self.ssip = Signal(name="mip_ssip")
 144         self.usip = Signal(name="mip_usip")
 145
 146         for n in dir(self):
 147             if n in ['make', 'comb', 'sync'] or n.startswith("_"):
 148                 continue
 149             self.comb += getattr(self, n).eq(0x0)
 150
 151     def make(self):
 152         return Cat( self.usip, self.ssip, 0, self.msip,
 153                     self.utip, self.stip, 0, self.mtip,
 154                     self.ueip, self.seip, 0, self.meip, )
 155
 156
 157 class M:
 158     def __init__(self, comb, sync):
 159         self.comb = comb
 160         self.sync = sync
 161         self.mcause = Signal(32)
 162         self.mepc = Signal(32)
 163         self.mscratch = Signal(32)
 164         self.sync += self.mcause.eq(0)
 165         self.sync += self.mepc.eq(0) # 32'hXXXXXXXX;
 166         self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
 167
 168
 169 class Misa:
 170     def __init__(self, comb, sync):
 171         self.comb = comb
 172         self.sync = sync
 173         self.misa = Signal(32)
 174         cl = []
 175         for l in list(string.ascii_lowercase):
 176             value = 1 if l == 'i' else 0
 177             cl.append(Constant(value))
 178         cl.append(Constant(0, 4))
 179         cl.append(Constant(0b01, 2))
 180         self.comb += self.misa.eq(Cat(cl))
 181
 182
 183 class Fetch:
 184     def __init__(self, comb, sync):
 185         self.comb = comb
 186         self.sync = sync
 187         self.action = Signal(fetch_action, name="fetch_action")
 188         self.target_pc = Signal(32, name="fetch_target_pc")
 189         self.output_pc = Signal(32, name="fetch_output_pc")
 190         self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
 191         self.output_state = Signal(fetch_output_state,name="fetch_output_state")
 192
 193 class CSR:
 194     def __init__(self, comb, sync, dc, register_rs1):
 195         self.comb = comb
 196         self.sync = sync
 197         self.number = Signal(12, name="csr_number")
 198         self.input_value = Signal(32, name="csr_input_value")
 199         self.reads = Signal(name="csr_reads")
 200         self.writes = Signal(name="csr_writes")
 201         self.op_is_valid = Signal(name="csr_op_is_valid")
 202
 203         self.comb += self.number.eq(dc.immediate)
 204         self.comb += self.input_value.eq(Mux(dc.funct3[2],
 205                                             dc.rs1,
 206                                             register_rs1))
 207         self.comb += self.reads.eq(dc.funct3[1] | (dc.rd != 0))
 208         self.comb += self.writes.eq(~dc.funct3[1] | (dc.rs1 != 0))
 209
 210         self.comb += self.get_csr_op_is_valid()
 211
 212     def get_csr_op_is_valid(self):
 213         """ determines if a CSR is valid
 214         """
 215         c = {}
 216         # invalid csrs
 217         for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr,
 218                   csr_uie, csr_utvec, csr_uscratch, csr_uepc,
 219                   csr_ucause, csr_utval, csr_uip, csr_sstatus,
 220                   csr_sedeleg, csr_sideleg, csr_sie, csr_stvec,
 221                   csr_scounteren, csr_sscratch, csr_sepc, csr_scause,
 222                   csr_stval, csr_sip, csr_satp, csr_medeleg,
 223                   csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]:
 224             c[f] = self.op_is_valid.eq(0)
 225
 226         # not-writeable -> ok
 227         for f in [csr_cycle, csr_time, csr_instret, csr_cycleh,
 228                   csr_timeh, csr_instreth, csr_mvendorid, csr_marchid,
 229                   csr_mimpid, csr_mhartid]:
 230             c[f] = self.op_is_valid.eq(~self.writes)
 231
 232         # valid csrs
 233         for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec,
 234                   csr_mscratch, csr_mepc, csr_mcause, csr_mip]:
 235             c[f] = self.op_is_valid.eq(1)
 236
 237         # not implemented / default
 238         for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret,
 239                   csr_mcycleh, csr_minstreth, "default"]:
 240             c[f] = self.op_is_valid.eq(0)
 241
 242         return Case(self.number, c)
 243
 244     def evaluate_csr_funct3_op(self, funct3, previous, written):
 245         c = { "default": written.eq(Constant(0, 32))}
 246         for f in [F3.csrrw, F3.csrrwi]:
 247             c[f] = written.eq(self.input_value)
 248         for f in [F3.csrrs, F3.csrrsi]:
 249             c[f] = written.eq(self.input_value | previous)
 250         for f in [F3.csrrc, F3.csrrci]:
 251             c[f] = written.eq(~self.input_value & previous)
 252         return Case(funct3, c)
 253
 254
 255 class MInfo:
 256     def __init__(self, comb):
 257         self.comb = comb
 258         # TODO
 259         self.cycle_counter   = Signal(64); # TODO: implement cycle_counter
 260         self.time_counter    = Signal(64); # TODO: implement time_counter
 261         self.instret_counter = Signal(64); # TODO: implement instret_counter
 262
 263         self.mvendorid = Signal(32)
 264         self.marchid = Signal(32)
 265         self.mimpid = Signal(32)
 266         self.mhartid = Signal(32)
 267         self.comb += self.mvendorid.eq(Constant(0, 32))
 268         self.comb += self.marchid.eq(Constant(0, 32))
 269         self.comb += self.mimpid.eq(Constant(0, 32))
 270         self.comb += self.mhartid.eq(Constant(0, 32))
 271
 272 class Regs:
 273     def __init__(self, comb, sync):
 274         self.comb = comb
 275         self.sync = sync
 276
 277         self.ra_en = Signal(reset=1, name="regfile_ra_en") # TODO: ondemand en
 278         self.rs1 = Signal(32, name="regfile_rs1")
 279         self.rs_a = Signal(5, name="regfile_rs_a")
 280
 281         self.rb_en = Signal(reset=1, name="regfile_rb_en") # TODO: ondemand en
 282         self.rs2 = Signal(32, name="regfile_rs2")
 283         self.rs_b = Signal(5, name="regfile_rs_b")
 284
 285         self.w_en = Signal(name="regfile_w_en")
 286         self.wval = Signal(32, name="regfile_wval")
 287         self.rd = Signal(32, name="regfile_rd")
 288
 289 class CPU(Module):
 290     """
 291     """
 292
 293     def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
 294         """ returns whether a load/store is misaligned
 295         """
 296         return Case(funct3[:2],
 297                 { F3.sb: ls.eq(Constant(0)),
 298                   F3.sh: ls.eq(load_store_address_low_2[0] != 0),
 299                   F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
 300                   "default": ls.eq(Constant(1))
 301                 })
 302
 303     def get_lsbm(self, dc):
 304         return Cat(Constant(1),
 305                    Mux((dc.funct3[1] | dc.funct3[0]),
 306                        Constant(1), Constant(0)),
 307                    Mux((dc.funct3[1]),
 308                        Constant(0b11, 2), Constant(0, 2)))
 309
 310     # XXX this happens to get done by various self.sync actions
 311     #def reset_to_initial(self, m, mstatus, mie, registers):
 312     #    return [m.mcause.eq(0),
 313     #            ]
 314
 315     def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
 316         s = [ms.mpie.eq(ms.mie),
 317              ms.mie.eq(0),
 318              m.mepc.eq(Mux(ft.action == FA.noerror_trap,
 319                            ft.output_pc + 4,
 320                            ft.output_pc))]
 321
 322         # fetch action ack trap
 323         i = If(ft.action == FA.ack_trap,
 324                 m.mcause.eq(cause_instruction_access_fault)
 325               )
 326
 327         # ecall/ebreak
 328         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
 329                 m.mcause.eq(Mux(dc.immediate[0],
 330                                 cause_machine_environment_call,
 331                                 cause_breakpoint))
 332               )
 333
 334         # load
 335         i = i.Elif((dc.act & DA.load) != 0,
 336                 If(load_store_misaligned,
 337                     m.mcause.eq(cause_load_address_misaligned)
 338                 ).Else(
 339                     m.mcause.eq(cause_load_access_fault)
 340                 )
 341               )
 342
 343         # store
 344         i = i.Elif((dc.act & DA.store) != 0,
 345                 If(load_store_misaligned,
 346                     m.mcause.eq(cause_store_amo_address_misaligned)
 347                 ).Else(
 348                     m.mcause.eq(cause_store_amo_access_fault)
 349                 )
 350               )
 351
 352         # jal/jalr -> misaligned=error, otherwise jump
 353         i = i.Elif((dc.act & (DA.jal | DA.jalr | DA.branch)) != 0,
 354                 m.mcause.eq(cause_instruction_address_misaligned)
 355               )
 356
 357         # defaults to illegal instruction
 358         i = i.Else(m.mcause.eq(cause_illegal_instruction))
 359
 360         s.append(i)
 361         return s
 362
 363     def main_block(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
 364                          ft, dc,
 365                          load_store_misaligned,
 366                          loaded_value, alu_result,
 367                          lui_auipc_result):
 368         c = {}
 369         c[FOS.empty] = []
 370         c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc,
 371                                        load_store_misaligned)
 372         c[FOS.valid] = self.handle_valid(mtvec, mip, minfo, misa, csr, mi, m,
 373                                        mstatus, mie, ft, dc,
 374                                        load_store_misaligned,
 375                                        loaded_value,
 376                                        alu_result,
 377                                        lui_auipc_result)
 378         return Case(ft.output_state, c)
 379
 380     def write_register(self, rd, val):
 381         return [self.regs.rd.eq(rd),
 382                 self.regs.wval.eq(val),
 383                 self.regs.w_en.eq(1)
 384                ]
 385
 386     def handle_valid(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
 387                            ft, dc,
 388                            load_store_misaligned,
 389                            loaded_value, alu_result,
 390                            lui_auipc_result):
 391         # fetch action ack trap
 392         i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
 393                 [self.handle_trap(m, mstatus, ft, dc,
 394                                        load_store_misaligned),
 395                  self.regs.w_en.eq(0) # no writing to registers
 396                 ]
 397               )
 398
 399         # load
 400         i = i.Elif((dc.act & DA.load) != 0,
 401                 If(~mi.rw_wait,
 402                     self.write_register(dc.rd, loaded_value)
 403                 )
 404               )
 405
 406         # op or op_immediate
 407         i = i.Elif((dc.act & DA.op_op_imm) != 0,
 408                 self.write_register(dc.rd, alu_result)
 409               )
 410
 411         # lui or auipc
 412         i = i.Elif((dc.act & DA.lui_auipc) != 0,
 413                 self.write_register(dc.rd, lui_auipc_result)
 414               )
 415
 416         # jal/jalr
 417         i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
 418                 self.write_register(dc.rd, ft.output_pc + 4)
 419               )
 420
 421         i = i.Elif((dc.act & DA.csr) != 0,
 422                 self.handle_csr(mtvec, mip, minfo, misa, mstatus, mie, m,
 423                                 dc, csr)
 424               )
 425
 426         # fence, store, branch
 427         i = i.Elif((dc.act & (DA.fence | DA.fence_i |
 428                               DA.store | DA.branch)) != 0,
 429                 # do nothing
 430                self.regs.w_en.eq(0) # no writing to registers
 431               )
 432
 433         return i
 434
 435     def handle_csr(self, mtvec, mip, minfo, misa, mstatus, mie, m, dc, csr):
 436         csr_output_value = Signal(32)
 437         csr_written_value = Signal(32)
 438         c = {}
 439
 440         # cycle
 441         c[csr_cycle]  = csr_output_value.eq(minfo.cycle_counter[0:32])
 442         c[csr_cycleh] = csr_output_value.eq(minfo.cycle_counter[32:64])
 443         # time
 444         c[csr_time]  = csr_output_value.eq(minfo.time_counter[0:32])
 445         c[csr_timeh] = csr_output_value.eq(minfo.time_counter[32:64])
 446         # instret
 447         c[csr_instret]  = csr_output_value.eq(minfo.instret_counter[0:32])
 448         c[csr_instreth] = csr_output_value.eq(minfo.instret_counter[32:64])
 449         # mvendorid/march/mimpl/mhart
 450         c[csr_mvendorid] = csr_output_value.eq(minfo.mvendorid)
 451         c[csr_marchid  ] = csr_output_value.eq(minfo.marchid  )
 452         c[csr_mimpid   ] = csr_output_value.eq(minfo.mimpid   )
 453         c[csr_mhartid  ] = csr_output_value.eq(minfo.mhartid  )
 454         # misa
 455         c[csr_misa     ] = csr_output_value.eq(misa.misa)
 456         # mstatus
 457         c[csr_mstatus  ] = [
 458             csr_output_value.eq(mstatus.make()),
 459             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 460                                                   csr_written_value),
 461             mstatus.mpie.eq(csr_written_value[7]),
 462             mstatus.mie.eq(csr_written_value[3])
 463         ]
 464         # mie
 465         c[csr_mie      ] = [
 466             csr_output_value.eq(mie.make()),
 467             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 468                                                   csr_written_value),
 469             mie.meie.eq(csr_written_value[11]),
 470             mie.mtie.eq(csr_written_value[7]),
 471             mie.msie.eq(csr_written_value[3]),
 472         ]
 473         # mtvec
 474         c[csr_mtvec    ] = csr_output_value.eq(mtvec)
 475         # mscratch
 476         c[csr_mscratch ] = [
 477             csr_output_value.eq(m.mscratch),
 478             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 479                                                   csr_written_value),
 480             If(csr.writes,
 481                 m.mscratch.eq(csr_written_value),
 482             )
 483         ]
 484         # mepc
 485         c[csr_mepc ] = [
 486             csr_output_value.eq(m.mepc),
 487             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 488                                                   csr_written_value),
 489             If(csr.writes,
 490                 m.mepc.eq(csr_written_value),
 491             )
 492         ]
 493
 494         # mcause
 495         c[csr_mcause ] = [
 496             csr_output_value.eq(m.mcause),
 497             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 498                                                   csr_written_value),
 499             If(csr.writes,
 500                 m.mcause.eq(csr_written_value),
 501             )
 502         ]
 503
 504         # mip
 505         c[csr_mip  ] = [
 506             csr_output_value.eq(mip.make()),
 507             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 508                                                   csr_written_value),
 509         ]
 510
 511         return [Case(csr.number, c),
 512                 If(csr.reads,
 513                     self.write_register(dc.rd, csr_output_value)
 514                 )]
 515
 516         """
 517                 `csr_mip: begin
 518                     csr_output_value = 0;
 519                     csr_output_value[11] = mip_meip;
 520                     csr_output_value[9] = mip_seip;
 521                     csr_output_value[8] = mip_ueip;
 522                     csr_output_value[7] = mip_mtip;
 523                     csr_output_value[5] = mip_stip;
 524                     csr_output_value[4] = mip_utip;
 525                     csr_output_value[3] = mip_msip;
 526                     csr_output_value[1] = mip_ssip;
 527                     csr_output_value[0] = mip_usip;
 528                 end
 529                 endcase
 530         end
 531         endcase
 532     end
 533         """
 534     def __init__(self):
 535         Module.__init__(self)
 536         self.clk = ClockSignal()
 537         self.reset = ResetSignal()
 538         self.tty_write = Signal()
 539         self.tty_write_data = Signal(8)
 540         self.tty_write_busy = Signal()
 541         self.switch_2 = Signal()
 542         self.switch_3 = Signal()
 543         self.led_1 = Signal()
 544         self.led_3 = Signal()
 545
 546         ram_size = Constant(0x8000)
 547         ram_start = Constant(0x10000, 32)
 548         reset_vector = Signal(32)
 549         mtvec = Signal(32)
 550
 551         reset_vector.eq(ram_start)
 552         mtvec.eq(ram_start + 0x40)
 553
 554         self.regs = Regs(self.comb, self.sync)
 555
 556         rf = Instance("RegFile", name="regfile",
 557            i_ra_en = self.regs.ra_en,
 558            i_rb_en = self.regs.rb_en,
 559            i_w_en = self.regs.w_en,
 560            o_read_a = self.regs.rs1,
 561            o_read_b = self.regs.rs2,
 562            i_writeval = self.regs.wval,
 563            i_rs_a = self.regs.rs_a,
 564            i_rs_b = self.regs.rs_b,
 565            i_rd = self.regs.rd)
 566
 567         self.specials += rf
 568
 569         mi = MemoryInterface()
 570
 571         mii = Instance("cpu_memory_interface", name="memory_instance",
 572                     p_ram_size = ram_size,
 573                     p_ram_start = ram_start,
 574                     i_clk=ClockSignal(),
 575                     i_rst=ResetSignal(),
 576                     i_fetch_address = mi.fetch_address,
 577                     o_fetch_data = mi.fetch_data,
 578                     o_fetch_valid = mi.fetch_valid,
 579                     i_rw_address = mi.rw_address,
 580                     i_rw_byte_mask = mi.rw_byte_mask,
 581                     i_rw_read_not_write = mi.rw_read_not_write,
 582                     i_rw_active = mi.rw_active,
 583                     i_rw_data_in = mi.rw_data_in,
 584                     o_rw_data_out = mi.rw_data_out,
 585                     o_rw_address_valid = mi.rw_address_valid,
 586                     o_rw_wait = mi.rw_wait,
 587                     o_tty_write = self.tty_write,
 588                     o_tty_write_data = self.tty_write_data,
 589                     i_tty_write_busy = self.tty_write_busy,
 590                     i_switch_2 = self.switch_2,
 591                     i_switch_3 = self.switch_3,
 592                     o_led_1 = self.led_1,
 593                     o_led_3 = self.led_3
 594                   )
 595         self.specials += mii
 596
 597         ft = Fetch(self.comb, self.sync)
 598
 599         fs = Instance("CPUFetchStage", name="fetch_stage",
 600             i_clk=ClockSignal(),
 601             i_rst=ResetSignal(),
 602             o_memory_interface_fetch_address = mi.fetch_address,
 603             i_memory_interface_fetch_data = mi.fetch_data,
 604             i_memory_interface_fetch_valid = mi.fetch_valid,
 605             i_fetch_action = ft.action,
 606             i_target_pc = ft.target_pc,
 607             o_output_pc = ft.output_pc,
 608             o_output_instruction = ft.output_instruction,
 609             o_output_state = ft.output_state,
 610             i_reset_vector = reset_vector,
 611             i_mtvec = mtvec,
 612         )
 613         self.specials += fs
 614
 615         dc = Decoder()
 616
 617         cd = Instance("CPUDecoder", name="decoder",
 618             i_instruction = ft.output_instruction,
 619             o_funct7 = dc.funct7,
 620             o_funct3 = dc.funct3,
 621             o_rd = dc.rd,
 622             o_rs1 = dc.rs1,
 623             o_rs2 = dc.rs2,
 624             o_immediate = dc.immediate,
 625             o_opcode = dc.opcode,
 626             o_decode_action = dc.act
 627         )
 628         self.specials += cd
 629
 630         self.comb += self.regs.rs_a.eq(dc.rs1)
 631         self.comb += self.regs.rs_b.eq(dc.rs2)
 632
 633         load_store_address = Signal(32)
 634         load_store_address_low_2 = Signal(2)
 635
 636         self.comb += load_store_address.eq(dc.immediate + self.regs.rs1)
 637         self.comb += load_store_address_low_2.eq(
 638                             dc.immediate[:2] + self.regs.rs1[:2])
 639
 640         load_store_misaligned = Signal()
 641
 642         lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3,
 643                                      load_store_address_low_2)
 644         self.comb += lsa
 645
 646         # XXX rwaddr not 31:2 any more
 647         self.comb += mi.rw_address.eq(load_store_address[2:])
 648
 649         unshifted_load_store_byte_mask = Signal(4)
 650
 651         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc))
 652
 653         # XXX yuck.  this will cause migen simulation to fail
 654         # (however conversion to verilog works)
 655         self.comb += mi.rw_byte_mask.eq(
 656                 _Operator("<<", [unshifted_load_store_byte_mask,
 657                                         load_store_address_low_2]))
 658
 659         # XXX not obvious
 660         b3 = Mux(load_store_address_low_2[1],
 661                  Mux(load_store_address_low_2[0], self.regs.rs2[0:8],
 662                                                   self.regs.rs2[8:16]),
 663                  Mux(load_store_address_low_2[0], self.regs.rs2[16:24],
 664                                                   self.regs.rs2[24:32]))
 665         b2 = Mux(load_store_address_low_2[1], self.regs.rs2[0:8],
 666                                               self.regs.rs2[16:24])
 667         b1 = Mux(load_store_address_low_2[0], self.regs.rs2[0:8],
 668                                               self.regs.rs2[8:16])
 669         b0 = self.regs.rs2[0:8]
 670
 671         self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
 672
 673         # XXX not obvious
 674         unmasked_loaded_value = Signal(32)
 675
 676         b0 = Mux(load_store_address_low_2[1],
 677                  Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
 678                                                   mi.rw_data_out[16:24]),
 679                  Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
 680                                                   mi.rw_data_out[0:8]))
 681         b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
 682                                               mi.rw_data_out[8:16])
 683         b23 = mi.rw_data_out[16:32]
 684
 685         self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
 686
 687         # XXX not obvious
 688         loaded_value = Signal(32)
 689
 690         b0 = unmasked_loaded_value[0:8]
 691         b1 = Mux(dc.funct3[0:2] == 0,
 692                 Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8),
 693                 unmasked_loaded_value[8:16])
 694         b2 = Mux(dc.funct3[1] == 0,
 695                 Replicate(~dc.funct3[2] &
 696                            Mux(dc.funct3[0], unmasked_loaded_value[15],
 697                                                   unmasked_loaded_value[7]),
 698                           16),
 699                 unmasked_loaded_value[16:32])
 700
 701         self.comb += loaded_value.eq(Cat(b0, b1, b2))
 702
 703         self.comb += mi.rw_active.eq(~self.reset
 704                         & (ft.output_state == FOS.valid)
 705                         & ~load_store_misaligned
 706                         & ((dc.act & (DA.load | DA.store)) != 0))
 707
 708         self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
 709
 710         # alu
 711         alu_a = Signal(32)
 712         alu_b = Signal(32)
 713         alu_result = Signal(32)
 714
 715         self.comb += alu_a.eq(self.regs.rs1)
 716         self.comb += alu_b.eq(Mux(dc.opcode[5],
 717                                   self.regs.rs2,
 718                                   dc.immediate))
 719
 720         ali = Instance("cpu_alu", name="alu",
 721             i_funct7 = dc.funct7,
 722             i_funct3 = dc.funct3,
 723             i_opcode = dc.opcode,
 724             i_a = alu_a,
 725             i_b = alu_b,
 726             o_result = alu_result
 727         )
 728         self.specials += ali
 729
 730         lui_auipc_result = Signal(32)
 731         self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
 732                                              dc.immediate,
 733                                              dc.immediate + ft.output_pc))
 734
 735         self.comb += ft.target_pc.eq(Cat(0,
 736                     Mux(dc.opcode != OP.jalr,
 737                                 ft.output_pc[1:32],
 738                                 self.regs.rs1[1:32] + dc.immediate[1:32])))
 739
 740         misaligned_jump_target = Signal()
 741         self.comb += misaligned_jump_target.eq(ft.target_pc[1])
 742
 743         branch_arg_a = Signal(32)
 744         branch_arg_b = Signal(32)
 745         self.comb += branch_arg_a.eq(Cat( self.regs.rs1[0:31],
 746                                           self.regs.rs1[31] ^ ~dc.funct3[1]))
 747         self.comb += branch_arg_b.eq(Cat( self.regs.rs2[0:31],
 748                                           self.regs.rs2[31] ^ ~dc.funct3[1]))
 749
 750         branch_taken = Signal()
 751         self.comb += branch_taken.eq(dc.funct3[0] ^
 752                                      Mux(dc.funct3[2],
 753                                          branch_arg_a < branch_arg_b,
 754                                          branch_arg_a == branch_arg_b))
 755
 756         m = M(self.comb, self.sync)
 757         mstatus = MStatus(self.comb, self.sync)
 758         mie = MIE(self.comb, self.sync)
 759         misa = Misa(self.comb, self.sync)
 760         mip = MIP(self.comb, self.sync)
 761
 762         # CSR decoding
 763         csr = CSR(self.comb, self.sync, dc, self.regs.rs1)
 764
 765         fi = Instance("CPUFetchAction", name="cpu_fetch_action",
 766             o_fetch_action = ft.action,
 767             i_output_state = ft.output_state,
 768             i_dc_act = dc.act,
 769             i_load_store_misaligned = load_store_misaligned,
 770             i_mi_rw_wait = mi.rw_wait,
 771             i_mi_rw_address_valid = mi.rw_address_valid,
 772             i_branch_taken = branch_taken,
 773             i_misaligned_jump_target = misaligned_jump_target,
 774             i_csr_op_is_valid = csr.op_is_valid)
 775
 776         self.specials += fi
 777
 778         minfo = MInfo(self.comb)
 779
 780         self.sync += If(~self.reset,
 781                         self.main_block(mtvec, mip, minfo, misa, csr, mi, m,
 782                                         mstatus, mie, ft, dc,
 783                                         load_store_misaligned,
 784                                         loaded_value,
 785                                        alu_result,
 786                                        lui_auipc_result)
 787                      )
 788
 789 if __name__ == "__main__":
 790     example = CPU()
 791     print(verilog.convert(example,
 792          {
 793            example.tty_write,
 794            example.tty_write_data,
 795            example.tty_write_busy,
 796            example.switch_2,
 797            example.switch_3,
 798            example.led_1,
 799            example.led_3,
 800            }))