3 * Copyright 2018 Jacob Lifshay
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in all
13 * copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 from migen
.fhdl
import verilog
32 from migen
.fhdl
.structure
import _Operator
34 from riscvdefs
import *
37 class MemoryInterface
:
38 fetch_address
= Signal(32, name
="memory_interface_fetch_address") # XXX [2:]
39 fetch_data
= Signal(32, name
="memory_interface_fetch_data")
40 fetch_valid
= Signal(name
="memory_interface_fetch_valid")
41 rw_address
= Signal(32, name
="memory_interface_rw_address") # XXX [2:]
42 rw_byte_mask
= Signal(4, name
="memory_interface_rw_byte_mask")
43 rw_read_not_write
= Signal(name
="memory_interface_rw_read_not_write")
44 rw_active
= Signal(name
="memory_interface_rw_active")
45 rw_data_in
= Signal(32, name
="memory_interface_rw_data_in")
46 rw_data_out
= Signal(32, name
="memory_interface_rw_data_out")
47 rw_address_valid
= Signal(name
="memory_interface_rw_address_valid")
48 rw_wait
= Signal(name
="memory_interface_rw_wait")
52 funct7
= Signal(7, name
="decoder_funct7")
53 funct3
= Signal(3, name
="decoder_funct3")
54 rd
= Signal(5, name
="decoder_rd")
55 rs1
= Signal(5, name
="decoder_rs1")
56 rs2
= Signal(5, name
="decoder_rs2")
57 immediate
= Signal(32, name
="decoder_immediate")
58 opcode
= Signal(7, name
="decoder_opcode")
59 act
= Signal(decode_action
, name
="decoder_action")
62 def __init__(self
, comb
, sync
):
65 self
.mpie
= Signal(name
="mstatus_mpie")
66 self
.mie
= Signal(name
="mstatus_mie")
67 self
.mprv
= Signal(name
="mstatus_mprv")
68 self
.tsr
= Signal(name
="mstatus_tsr")
69 self
.tw
= Signal(name
="mstatus_tw")
70 self
.tvm
= Signal(name
="mstatus_tvm")
71 self
.mxr
= Signal(name
="mstatus_mxr")
72 self
._sum
= Signal(name
="mstatus_sum")
73 self
.xs
= Signal(name
="mstatus_xs")
74 self
.fs
= Signal(name
="mstatus_fs")
75 self
.mpp
= Signal(2, name
="mstatus_mpp")
76 self
.spp
= Signal(name
="mstatus_spp")
77 self
.spie
= Signal(name
="mstatus_spie")
78 self
.upie
= Signal(name
="mstatus_upie")
79 self
.sie
= Signal(name
="mstatus_sie")
80 self
.uie
= Signal(name
="mstatus_uie")
83 if n
in ['make', 'mpp', 'comb', 'sync'] or n
.startswith("_"):
85 self
.comb
+= getattr(self
, n
).eq(0x0)
86 self
.comb
+= self
.mpp
.eq(0b11)
88 self
.sync
+= self
.mie
.eq(0)
89 self
.sync
+= self
.mpie
.eq(0)
93 self
.uie
, self
.sie
, Constant(0), self
.mie
,
94 self
.upie
, self
.spie
, Constant(0), self
.mpie
,
95 self
.spp
, Constant(0, 2), self
.mpp
,
96 self
.fs
, self
.xs
, self
.mprv
, self
._sum
,
97 self
.mxr
, self
.tvm
, self
.tw
, self
.tsr
,
99 (self
.xs
== Constant(0b11, 2)) |
(self
.fs
== Constant(0b11, 2))
104 def __init__(self
, comb
, sync
):
107 self
.meie
= Signal(name
="mie_meie")
108 self
.mtie
= Signal(name
="mie_mtie")
109 self
.msie
= Signal(name
="mie_msie")
110 self
.seie
= Signal(name
="mie_seie")
111 self
.ueie
= Signal(name
="mie_ueie")
112 self
.stie
= Signal(name
="mie_stie")
113 self
.utie
= Signal(name
="mie_utie")
114 self
.ssie
= Signal(name
="mie_ssie")
115 self
.usie
= Signal(name
="mie_usie")
118 if n
in ['make', 'comb', 'sync'] or n
.startswith("_"):
120 self
.comb
+= getattr(self
, n
).eq(0x0)
122 self
.sync
+= self
.meie
.eq(0)
123 self
.sync
+= self
.mtie
.eq(0)
124 self
.sync
+= self
.msie
.eq(0)
127 return Cat( self
.usie
, self
.ssie
, 0, self
.msie
,
128 self
.utie
, self
.stie
, 0, self
.mtie
,
129 self
.ueie
, self
.seie
, 0, self
.meie
, )
133 def __init__(self
, comb
, sync
):
136 self
.meip
= Signal(name
="mip_meip") # TODO: implement ext interrupts
137 self
.seip
= Signal(name
="mip_seip")
138 self
.ueip
= Signal(name
="mip_uiep")
139 self
.mtip
= Signal(name
="mip_mtip") # TODO: implement timer interrupts
140 self
.stip
= Signal(name
="mip_stip")
141 self
.msip
= Signal(name
="mip_stip")
142 self
.utip
= Signal(name
="mip_utip")
143 self
.ssip
= Signal(name
="mip_ssip")
144 self
.usip
= Signal(name
="mip_usip")
147 if n
in ['make', 'comb', 'sync'] or n
.startswith("_"):
149 self
.comb
+= getattr(self
, n
).eq(0x0)
152 return Cat( self
.usip
, self
.ssip
, 0, self
.msip
,
153 self
.utip
, self
.stip
, 0, self
.mtip
,
154 self
.ueip
, self
.seip
, 0, self
.meip
, )
158 def __init__(self
, comb
, sync
):
161 self
.mcause
= Signal(32)
162 self
.mepc
= Signal(32)
163 self
.mscratch
= Signal(32)
164 self
.sync
+= self
.mcause
.eq(0)
165 self
.sync
+= self
.mepc
.eq(0) # 32'hXXXXXXXX;
166 self
.sync
+= self
.mscratch
.eq(0) # 32'hXXXXXXXX;
170 def __init__(self
, comb
, sync
):
173 self
.misa
= Signal(32)
175 for l
in list(string
.ascii_lowercase
):
176 value
= 1 if l
== 'i' else 0
177 cl
.append(Constant(value
))
178 cl
.append(Constant(0, 4))
179 cl
.append(Constant(0b01, 2))
180 self
.comb
+= self
.misa
.eq(Cat(cl
))
184 def __init__(self
, comb
, sync
):
187 self
.action
= Signal(fetch_action
, name
="fetch_action")
188 self
.target_pc
= Signal(32, name
="fetch_target_pc")
189 self
.output_pc
= Signal(32, name
="fetch_output_pc")
190 self
.output_instruction
= Signal(32, name
="fetch_ouutput_instruction")
191 self
.output_state
= Signal(fetch_output_state
,name
="fetch_output_state")
193 def get_fetch_action(self
, dc
, load_store_misaligned
, mi
,
194 branch_taken
, misaligned_jump_target
,
197 c
["default"] = self
.action
.eq(FA
.default
) # XXX should be 32'XXXXXXXX?
198 c
[FOS
.empty
] = self
.action
.eq(FA
.default
)
199 c
[FOS
.trap
] = self
.action
.eq(FA
.ack_trap
)
201 # illegal instruction -> error trap
202 i
= If((dc
.act
& DA
.trap_illegal_instruction
) != 0,
203 self
.action
.eq(FA
.error_trap
)
206 # ecall / ebreak -> noerror trap
207 i
= i
.Elif((dc
.act
& DA
.trap_ecall_ebreak
) != 0,
208 self
.action
.eq(FA
.noerror_trap
))
210 # load/store: check alignment, check wait
211 i
= i
.Elif((dc
.act
& (DA
.load | DA
.store
)) != 0,
212 If((load_store_misaligned | ~mi
.rw_address_valid
),
213 self
.action
.eq(FA
.error_trap
) # misaligned or invalid addr
215 self
.action
.eq(FA
.wait
) # wait
217 self
.action
.eq(FA
.default
) # ok
222 i
= i
.Elif((dc
.act
& DA
.fence
) != 0,
223 self
.action
.eq(FA
.fence
))
225 # branch -> misaligned=error, otherwise jump
226 i
= i
.Elif((dc
.act
& DA
.branch
) != 0,
227 If(misaligned_jump_target
,
228 self
.action
.eq(FA
.error_trap
)
230 self
.action
.eq(FA
.jump
)
234 # jal/jalr -> misaligned=error, otherwise jump
235 i
= i
.Elif((dc
.act
& (DA
.jal | DA
.jalr
)) != 0,
236 If(misaligned_jump_target
,
237 self
.action
.eq(FA
.error_trap
)
239 self
.action
.eq(FA
.jump
)
243 # csr -> opvalid=ok, else error trap
244 i
= i
.Elif((dc
.act
& DA
.csr
) != 0,
246 self
.action
.eq(FA
.default
)
248 self
.action
.eq(FA
.error_trap
)
254 return Case(self
.output_state
, c
)
257 def __init__(self
, comb
, sync
, dc
, register_rs1
):
260 self
.number
= Signal(12, name
="csr_number")
261 self
.input_value
= Signal(32, name
="csr_input_value")
262 self
.reads
= Signal(name
="csr_reads")
263 self
.writes
= Signal(name
="csr_writes")
264 self
.op_is_valid
= Signal(name
="csr_op_is_valid")
266 self
.comb
+= self
.number
.eq(dc
.immediate
)
267 self
.comb
+= self
.input_value
.eq(Mux(dc
.funct3
[2],
270 self
.comb
+= self
.reads
.eq(dc
.funct3
[1] |
(dc
.rd
!= 0))
271 self
.comb
+= self
.writes
.eq(~dc
.funct3
[1] |
(dc
.rs1
!= 0))
273 self
.comb
+= self
.get_csr_op_is_valid()
275 def get_csr_op_is_valid(self
):
276 """ determines if a CSR is valid
280 for f
in [csr_ustatus
, csr_fflags
, csr_frm
, csr_fcsr
,
281 csr_uie
, csr_utvec
, csr_uscratch
, csr_uepc
,
282 csr_ucause
, csr_utval
, csr_uip
, csr_sstatus
,
283 csr_sedeleg
, csr_sideleg
, csr_sie
, csr_stvec
,
284 csr_scounteren
, csr_sscratch
, csr_sepc
, csr_scause
,
285 csr_stval
, csr_sip
, csr_satp
, csr_medeleg
,
286 csr_mideleg
, csr_dcsr
, csr_dpc
, csr_dscratch
]:
287 c
[f
] = self
.op_is_valid
.eq(0)
289 # not-writeable -> ok
290 for f
in [csr_cycle
, csr_time
, csr_instret
, csr_cycleh
,
291 csr_timeh
, csr_instreth
, csr_mvendorid
, csr_marchid
,
292 csr_mimpid
, csr_mhartid
]:
293 c
[f
] = self
.op_is_valid
.eq(~self
.writes
)
296 for f
in [csr_misa
, csr_mstatus
, csr_mie
, csr_mtvec
,
297 csr_mscratch
, csr_mepc
, csr_mcause
, csr_mip
]:
298 c
[f
] = self
.op_is_valid
.eq(1)
300 # not implemented / default
301 for f
in [csr_mcounteren
, csr_mtval
, csr_mcycle
, csr_minstret
,
302 csr_mcycleh
, csr_minstreth
, "default"]:
303 c
[f
] = self
.op_is_valid
.eq(0)
305 return Case(self
.number
, c
)
307 def evaluate_csr_funct3_op(self
, funct3
, previous
, written
):
308 c
= { "default": written
.eq(Constant(0, 32))}
309 for f
in [F3
.csrrw
, F3
.csrrwi
]:
310 c
[f
] = written
.eq(self
.input_value
)
311 for f
in [F3
.csrrs
, F3
.csrrsi
]:
312 c
[f
] = written
.eq(self
.input_value | previous
)
313 for f
in [F3
.csrrc
, F3
.csrrci
]:
314 c
[f
] = written
.eq(~self
.input_value
& previous
)
315 return Case(funct3
, c
)
319 def __init__(self
, comb
):
322 self
.cycle_counter
= Signal(64); # TODO: implement cycle_counter
323 self
.time_counter
= Signal(64); # TODO: implement time_counter
324 self
.instret_counter
= Signal(64); # TODO: implement instret_counter
326 self
.mvendorid
= Signal(32)
327 self
.marchid
= Signal(32)
328 self
.mimpid
= Signal(32)
329 self
.mhartid
= Signal(32)
330 self
.comb
+= self
.mvendorid
.eq(Constant(0, 32))
331 self
.comb
+= self
.marchid
.eq(Constant(0, 32))
332 self
.comb
+= self
.mimpid
.eq(Constant(0, 32))
333 self
.comb
+= self
.mhartid
.eq(Constant(0, 32))
336 def __init__(self
, comb
, sync
):
340 self
.ra_en
= Signal(reset
=1)
341 self
.rb_en
= Signal(reset
=1)
342 self
.wen
= Signal(name
="register_wen")
344 self
.rs1
= Signal(32, name
="register_rs1")
345 self
.rs2
= Signal(32, name
="register_rs2")
346 self
.wval
= Signal(32, name
="register_wval")
348 self
.rs_a
= Signal(5, name
="register_rs_a")
349 self
.rs_b
= Signal(5, name
="register_rs_b")
350 self
.rd
= Signal(32, name
="register_rd")
356 def get_ls_misaligned(self
, ls
, funct3
, load_store_address_low_2
):
357 """ returns whether a load/store is misaligned
359 return Case(funct3
[:2],
360 { F3
.sb
: ls
.eq(Constant(0)),
361 F3
.sh
: ls
.eq(load_store_address_low_2
[0] != 0),
362 F3
.sw
: ls
.eq(load_store_address_low_2
[0:2] != Constant(0, 2)),
363 "default": ls
.eq(Constant(1))
366 def get_lsbm(self
, dc
):
367 return Cat(Constant(1),
368 Mux((dc
.funct3
[1] | dc
.funct3
[0]),
369 Constant(1), Constant(0)),
371 Constant(0b11, 2), Constant(0, 2)))
373 # XXX this happens to get done by various self.sync actions
374 #def reset_to_initial(self, m, mstatus, mie, registers):
375 # return [m.mcause.eq(0),
378 def handle_trap(self
, m
, ms
, ft
, dc
, load_store_misaligned
):
379 s
= [ms
.mpie
.eq(ms
.mie
),
381 m
.mepc
.eq(Mux(ft
.action
== FA
.noerror_trap
,
385 # fetch action ack trap
386 i
= If(ft
.action
== FA
.ack_trap
,
387 m
.mcause
.eq(cause_instruction_access_fault
)
391 i
= i
.Elif((dc
.act
& DA
.trap_ecall_ebreak
) != 0,
392 m
.mcause
.eq(Mux(dc
.immediate
[0],
393 cause_machine_environment_call
,
398 i
= i
.Elif((dc
.act
& DA
.load
) != 0,
399 If(load_store_misaligned
,
400 m
.mcause
.eq(cause_load_address_misaligned
)
402 m
.mcause
.eq(cause_load_access_fault
)
407 i
= i
.Elif((dc
.act
& DA
.store
) != 0,
408 If(load_store_misaligned
,
409 m
.mcause
.eq(cause_store_amo_address_misaligned
)
411 m
.mcause
.eq(cause_store_amo_access_fault
)
415 # jal/jalr -> misaligned=error, otherwise jump
416 i
= i
.Elif((dc
.act
& (DA
.jal | DA
.jalr | DA
.branch
)) != 0,
417 m
.mcause
.eq(cause_instruction_address_misaligned
)
420 # defaults to illegal instruction
421 i
= i
.Else(m
.mcause
.eq(cause_illegal_instruction
))
426 def main_block(self
, mtvec
, mip
, minfo
, misa
, csr
, mi
, m
, mstatus
, mie
,
428 load_store_misaligned
,
429 loaded_value
, alu_result
,
433 c
[FOS
.trap
] = self
.handle_trap(m
, mstatus
, ft
, dc
,
434 load_store_misaligned
)
435 c
[FOS
.valid
] = self
.handle_valid(mtvec
, mip
, minfo
, misa
, csr
, mi
, m
,
436 mstatus
, mie
, ft
, dc
,
437 load_store_misaligned
,
441 return Case(ft
.output_state
, c
)
443 def write_register(self
, rd
, val
):
444 return [self
.regs
.rd
.eq(rd
),
445 self
.regs
.wval
.eq(val
),
449 def handle_valid(self
, mtvec
, mip
, minfo
, misa
, csr
, mi
, m
, mstatus
, mie
,
451 load_store_misaligned
,
452 loaded_value
, alu_result
,
454 # fetch action ack trap
455 i
= If((ft
.action
== FA
.ack_trap
) |
(ft
.action
== FA
.noerror_trap
),
456 [self
.handle_trap(m
, mstatus
, ft
, dc
,
457 load_store_misaligned
),
458 self
.regs
.wen
.eq(0) # no writing to registers
463 i
= i
.Elif((dc
.act
& DA
.load
) != 0,
465 self
.write_register(dc
.rd
, loaded_value
)
470 i
= i
.Elif((dc
.act
& DA
.op_op_imm
) != 0,
471 self
.write_register(dc
.rd
, alu_result
)
475 i
= i
.Elif((dc
.act
& DA
.lui_auipc
) != 0,
476 self
.write_register(dc
.rd
, lui_auipc_result
)
480 i
= i
.Elif((dc
.act
& (DA
.jal | DA
.jalr
)) != 0,
481 self
.write_register(dc
.rd
, ft
.output_pc
+ 4)
484 i
= i
.Elif((dc
.act
& DA
.csr
) != 0,
485 self
.handle_csr(mtvec
, mip
, minfo
, misa
, mstatus
, mie
, m
,
489 # fence, store, branch
490 i
= i
.Elif((dc
.act
& (DA
.fence | DA
.fence_i |
491 DA
.store | DA
.branch
)) != 0,
493 self
.regs
.wen
.eq(0) # no writing to registers
498 def handle_csr(self
, mtvec
, mip
, minfo
, misa
, mstatus
, mie
, m
, dc
, csr
):
499 csr_output_value
= Signal(32)
500 csr_written_value
= Signal(32)
504 c
[csr_cycle
] = csr_output_value
.eq(minfo
.cycle_counter
[0:32])
505 c
[csr_cycleh
] = csr_output_value
.eq(minfo
.cycle_counter
[32:64])
507 c
[csr_time
] = csr_output_value
.eq(minfo
.time_counter
[0:32])
508 c
[csr_timeh
] = csr_output_value
.eq(minfo
.time_counter
[32:64])
510 c
[csr_instret
] = csr_output_value
.eq(minfo
.instret_counter
[0:32])
511 c
[csr_instreth
] = csr_output_value
.eq(minfo
.instret_counter
[32:64])
512 # mvendorid/march/mimpl/mhart
513 c
[csr_mvendorid
] = csr_output_value
.eq(minfo
.mvendorid
)
514 c
[csr_marchid
] = csr_output_value
.eq(minfo
.marchid
)
515 c
[csr_mimpid
] = csr_output_value
.eq(minfo
.mimpid
)
516 c
[csr_mhartid
] = csr_output_value
.eq(minfo
.mhartid
)
518 c
[csr_misa
] = csr_output_value
.eq(misa
.misa
)
521 csr_output_value
.eq(mstatus
.make()),
522 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
524 mstatus
.mpie
.eq(csr_written_value
[7]),
525 mstatus
.mie
.eq(csr_written_value
[3])
529 csr_output_value
.eq(mie
.make()),
530 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
532 mie
.meie
.eq(csr_written_value
[11]),
533 mie
.mtie
.eq(csr_written_value
[7]),
534 mie
.msie
.eq(csr_written_value
[3]),
537 c
[csr_mtvec
] = csr_output_value
.eq(mtvec
)
540 csr_output_value
.eq(m
.mscratch
),
541 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
544 m
.mscratch
.eq(csr_written_value
),
549 csr_output_value
.eq(m
.mepc
),
550 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
553 m
.mepc
.eq(csr_written_value
),
559 csr_output_value
.eq(m
.mcause
),
560 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
563 m
.mcause
.eq(csr_written_value
),
569 csr_output_value
.eq(mip
.make()),
570 csr
.evaluate_csr_funct3_op(dc
.funct3
, csr_output_value
,
574 return [Case(csr
.number
, c
),
576 self
.write_register(dc
.rd
, csr_output_value
)
581 csr_output_value = 0;
582 csr_output_value[11] = mip_meip;
583 csr_output_value[9] = mip_seip;
584 csr_output_value[8] = mip_ueip;
585 csr_output_value[7] = mip_mtip;
586 csr_output_value[5] = mip_stip;
587 csr_output_value[4] = mip_utip;
588 csr_output_value[3] = mip_msip;
589 csr_output_value[1] = mip_ssip;
590 csr_output_value[0] = mip_usip;
598 Module
.__init
__(self
)
599 self
.clk
= ClockSignal()
600 self
.reset
= ResetSignal()
601 self
.tty_write
= Signal()
602 self
.tty_write_data
= Signal(8)
603 self
.tty_write_busy
= Signal()
604 self
.switch_2
= Signal()
605 self
.switch_3
= Signal()
606 self
.led_1
= Signal()
607 self
.led_3
= Signal()
609 ram_size
= Constant(0x8000)
610 ram_start
= Constant(0x10000, 32)
611 reset_vector
= Signal(32)
614 reset_vector
.eq(ram_start
)
615 mtvec
.eq(ram_start
+ 0x40)
617 self
.regs
= Regs(self
.comb
, self
.sync
)
619 rf
= Instance("RegFile", name
="regfile",
620 i_ra_en
= self
.regs
.ra_en
,
621 i_rb_en
= self
.regs
.rb_en
,
622 i_w_en
= self
.regs
.wen
,
623 o_read_a
= self
.regs
.rs1
,
624 o_read_b
= self
.regs
.rs2
,
625 i_writeval
= self
.regs
.wval
,
626 i_rs_a
= self
.regs
.rs_a
,
627 i_rs_b
= self
.regs
.rs_b
,
632 mi
= MemoryInterface()
634 mii
= Instance("cpu_memory_interface", name
="memory_instance",
635 p_ram_size
= ram_size
,
636 p_ram_start
= ram_start
,
639 i_fetch_address
= mi
.fetch_address
,
640 o_fetch_data
= mi
.fetch_data
,
641 o_fetch_valid
= mi
.fetch_valid
,
642 i_rw_address
= mi
.rw_address
,
643 i_rw_byte_mask
= mi
.rw_byte_mask
,
644 i_rw_read_not_write
= mi
.rw_read_not_write
,
645 i_rw_active
= mi
.rw_active
,
646 i_rw_data_in
= mi
.rw_data_in
,
647 o_rw_data_out
= mi
.rw_data_out
,
648 o_rw_address_valid
= mi
.rw_address_valid
,
649 o_rw_wait
= mi
.rw_wait
,
650 o_tty_write
= self
.tty_write
,
651 o_tty_write_data
= self
.tty_write_data
,
652 i_tty_write_busy
= self
.tty_write_busy
,
653 i_switch_2
= self
.switch_2
,
654 i_switch_3
= self
.switch_3
,
655 o_led_1
= self
.led_1
,
660 ft
= Fetch(self
.comb
, self
.sync
)
662 fs
= Instance("CPUFetchStage", name
="fetch_stage",
665 o_memory_interface_fetch_address
= mi
.fetch_address
,
666 i_memory_interface_fetch_data
= mi
.fetch_data
,
667 i_memory_interface_fetch_valid
= mi
.fetch_valid
,
668 i_fetch_action
= ft
.action
,
669 i_target_pc
= ft
.target_pc
,
670 o_output_pc
= ft
.output_pc
,
671 o_output_instruction
= ft
.output_instruction
,
672 o_output_state
= ft
.output_state
,
673 i_reset_vector
= reset_vector
,
680 cd
= Instance("CPUDecoder", name
="decoder",
681 i_instruction
= ft
.output_instruction
,
682 o_funct7
= dc
.funct7
,
683 o_funct3
= dc
.funct3
,
687 o_immediate
= dc
.immediate
,
688 o_opcode
= dc
.opcode
,
689 o_decode_action
= dc
.act
693 self
.comb
+= self
.regs
.rs_a
.eq(dc
.rs1
)
694 self
.comb
+= self
.regs
.rs_b
.eq(dc
.rs2
)
696 load_store_address
= Signal(32)
697 load_store_address_low_2
= Signal(2)
699 self
.comb
+= load_store_address
.eq(dc
.immediate
+ self
.regs
.rs1
)
700 self
.comb
+= load_store_address_low_2
.eq(
701 dc
.immediate
[:2] + self
.regs
.rs1
[:2])
703 load_store_misaligned
= Signal()
705 lsa
= self
.get_ls_misaligned(load_store_misaligned
, dc
.funct3
,
706 load_store_address_low_2
)
709 # XXX rwaddr not 31:2 any more
710 self
.comb
+= mi
.rw_address
.eq(load_store_address
[2:])
712 unshifted_load_store_byte_mask
= Signal(4)
714 self
.comb
+= unshifted_load_store_byte_mask
.eq(self
.get_lsbm(dc
))
716 # XXX yuck. this will cause migen simulation to fail
717 # (however conversion to verilog works)
718 self
.comb
+= mi
.rw_byte_mask
.eq(
719 _Operator("<<", [unshifted_load_store_byte_mask
,
720 load_store_address_low_2
]))
723 b3
= Mux(load_store_address_low_2
[1],
724 Mux(load_store_address_low_2
[0], self
.regs
.rs2
[0:8],
725 self
.regs
.rs2
[8:16]),
726 Mux(load_store_address_low_2
[0], self
.regs
.rs2
[16:24],
727 self
.regs
.rs2
[24:32]))
728 b2
= Mux(load_store_address_low_2
[1], self
.regs
.rs2
[0:8],
729 self
.regs
.rs2
[16:24])
730 b1
= Mux(load_store_address_low_2
[0], self
.regs
.rs2
[0:8],
732 b0
= self
.regs
.rs2
[0:8]
734 self
.comb
+= mi
.rw_data_in
.eq(Cat(b0
, b1
, b2
, b3
))
737 unmasked_loaded_value
= Signal(32)
739 b0
= Mux(load_store_address_low_2
[1],
740 Mux(load_store_address_low_2
[0], mi
.rw_data_out
[24:32],
741 mi
.rw_data_out
[16:24]),
742 Mux(load_store_address_low_2
[0], mi
.rw_data_out
[15:8],
743 mi
.rw_data_out
[0:8]))
744 b1
= Mux(load_store_address_low_2
[1], mi
.rw_data_out
[24:31],
745 mi
.rw_data_out
[8:16])
746 b23
= mi
.rw_data_out
[16:32]
748 self
.comb
+= unmasked_loaded_value
.eq(Cat(b0
, b1
, b23
))
751 loaded_value
= Signal(32)
753 b0
= unmasked_loaded_value
[0:8]
754 b1
= Mux(dc
.funct3
[0:2] == 0,
755 Replicate(~dc
.funct3
[2] & unmasked_loaded_value
[7], 8),
756 unmasked_loaded_value
[8:16])
757 b2
= Mux(dc
.funct3
[1] == 0,
758 Replicate(~dc
.funct3
[2] &
759 Mux(dc
.funct3
[0], unmasked_loaded_value
[15],
760 unmasked_loaded_value
[7]),
762 unmasked_loaded_value
[16:32])
764 self
.comb
+= loaded_value
.eq(Cat(b0
, b1
, b2
))
766 self
.comb
+= mi
.rw_active
.eq(~self
.reset
767 & (ft
.output_state
== FOS
.valid
)
768 & ~load_store_misaligned
769 & ((dc
.act
& (DA
.load | DA
.store
)) != 0))
771 self
.comb
+= mi
.rw_read_not_write
.eq(~dc
.opcode
[5])
776 alu_result
= Signal(32)
778 self
.comb
+= alu_a
.eq(self
.regs
.rs1
)
779 self
.comb
+= alu_b
.eq(Mux(dc
.opcode
[5],
783 ali
= Instance("cpu_alu", name
="alu",
784 i_funct7
= dc
.funct7
,
785 i_funct3
= dc
.funct3
,
786 i_opcode
= dc
.opcode
,
789 o_result
= alu_result
793 lui_auipc_result
= Signal(32)
794 self
.comb
+= lui_auipc_result
.eq(Mux(dc
.opcode
[5],
796 dc
.immediate
+ ft
.output_pc
))
798 self
.comb
+= ft
.target_pc
.eq(Cat(0,
799 Mux(dc
.opcode
!= OP
.jalr
,
801 self
.regs
.rs1
[1:32] + dc
.immediate
[1:32])))
803 misaligned_jump_target
= Signal()
804 self
.comb
+= misaligned_jump_target
.eq(ft
.target_pc
[1])
806 branch_arg_a
= Signal(32)
807 branch_arg_b
= Signal(32)
808 self
.comb
+= branch_arg_a
.eq(Cat( self
.regs
.rs1
[0:31],
809 self
.regs
.rs1
[31] ^ ~dc
.funct3
[1]))
810 self
.comb
+= branch_arg_b
.eq(Cat( self
.regs
.rs2
[0:31],
811 self
.regs
.rs2
[31] ^ ~dc
.funct3
[1]))
813 branch_taken
= Signal()
814 self
.comb
+= branch_taken
.eq(dc
.funct3
[0] ^
816 branch_arg_a
< branch_arg_b
,
817 branch_arg_a
== branch_arg_b
))
819 m
= M(self
.comb
, self
.sync
)
820 mstatus
= MStatus(self
.comb
, self
.sync
)
821 mie
= MIE(self
.comb
, self
.sync
)
822 misa
= Misa(self
.comb
, self
.sync
)
823 mip
= MIP(self
.comb
, self
.sync
)
826 csr
= CSR(self
.comb
, self
.sync
, dc
, self
.regs
.rs1
)
828 self
.comb
+= ft
.get_fetch_action(dc
, load_store_misaligned
, mi
,
829 branch_taken
, misaligned_jump_target
,
832 minfo
= MInfo(self
.comb
)
834 self
.sync
+= If(~self
.reset
,
835 self
.main_block(mtvec
, mip
, minfo
, misa
, csr
, mi
, m
,
836 mstatus
, mie
, ft
, dc
,
837 load_store_misaligned
,
843 if __name__
== "__main__":
845 print(verilog
.convert(example
,
848 example
.tty_write_data
,
849 example
.tty_write_busy
,