cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 import string
  30 from migen import *
  31 from migen.fhdl import verilog
  32 from migen.fhdl.structure import _Operator
  33
  34 from riscvdefs import *
  35 from cpudefs import *
  36
  37 class MemoryInterface:
  38     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  39     fetch_data = Signal(32, name="memory_interface_fetch_data")
  40     fetch_valid = Signal(name="memory_interface_fetch_valid")
  41     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  42     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  43     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  44     rw_active = Signal(name="memory_interface_rw_active")
  45     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  46     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  47     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  48     rw_wait = Signal(name="memory_interface_rw_wait")
  49
  50
  51 class Decoder:
  52     funct7 = Signal(7, name="decoder_funct7")
  53     funct3 = Signal(3, name="decoder_funct3")
  54     rd = Signal(5, name="decoder_rd")
  55     rs1 = Signal(5, name="decoder_rs1")
  56     rs2 = Signal(5, name="decoder_rs2")
  57     immediate = Signal(32, name="decoder_immediate")
  58     opcode = Signal(7, name="decoder_opcode")
  59     act = Signal(decode_action, name="decoder_action")
  60
  61 class MStatus:
  62     def __init__(self, comb, sync):
  63         self.comb = comb
  64         self.sync = sync
  65         self.mpie = Signal(name="mstatus_mpie")
  66         self.mie = Signal(name="mstatus_mie")
  67         self.mprv = Signal(name="mstatus_mprv")
  68         self.tsr = Signal(name="mstatus_tsr")
  69         self.tw = Signal(name="mstatus_tw")
  70         self.tvm = Signal(name="mstatus_tvm")
  71         self.mxr = Signal(name="mstatus_mxr")
  72         self._sum = Signal(name="mstatus_sum")
  73         self.xs = Signal(name="mstatus_xs")
  74         self.fs = Signal(name="mstatus_fs")
  75         self.mpp = Signal(2, name="mstatus_mpp")
  76         self.spp = Signal(name="mstatus_spp")
  77         self.spie = Signal(name="mstatus_spie")
  78         self.upie = Signal(name="mstatus_upie")
  79         self.sie = Signal(name="mstatus_sie")
  80         self.uie = Signal(name="mstatus_uie")
  81
  82         for n in dir(self):
  83             if n in ['make', 'mpp', 'comb', 'sync'] or n.startswith("_"):
  84                 continue
  85             self.comb += getattr(self, n).eq(0x0)
  86         self.comb += self.mpp.eq(0b11)
  87
  88         self.sync += self.mie.eq(0)
  89         self.sync += self.mpie.eq(0)
  90
  91     def make(self):
  92         return Cat(
  93                 self.uie, self.sie, Constant(0), self.mie,
  94                 self.upie, self.spie, Constant(0), self.mpie,
  95                 self.spp, Constant(0, 2), self.mpp,
  96                 self.fs, self.xs, self.mprv, self._sum,
  97                 self.mxr, self.tvm, self.tw, self.tsr,
  98                 Constant(0, 8),
  99                 (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2))
 100                 )
 101
 102
 103 class MIE:
 104     def __init__(self, comb, sync):
 105         self.comb = comb
 106         self.sync = sync
 107         self.meie = Signal(name="mie_meie")
 108         self.mtie = Signal(name="mie_mtie")
 109         self.msie = Signal(name="mie_msie")
 110         self.seie = Signal(name="mie_seie")
 111         self.ueie = Signal(name="mie_ueie")
 112         self.stie = Signal(name="mie_stie")
 113         self.utie = Signal(name="mie_utie")
 114         self.ssie = Signal(name="mie_ssie")
 115         self.usie = Signal(name="mie_usie")
 116
 117         for n in dir(self):
 118             if n in ['make', 'comb', 'sync'] or n.startswith("_"):
 119                 continue
 120             self.comb += getattr(self, n).eq(0x0)
 121
 122         self.sync += self.meie.eq(0)
 123         self.sync += self.mtie.eq(0)
 124         self.sync += self.msie.eq(0)
 125
 126     def make(self):
 127         return Cat( self.usie, self.ssie, 0, self.msie,
 128                     self.utie, self.stie, 0, self.mtie,
 129                     self.ueie, self.seie, 0, self.meie, )
 130
 131
 132 class MIP:
 133     def __init__(self, comb, sync):
 134         self.comb = comb
 135         self.sync = sync
 136         self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts
 137         self.seip = Signal(name="mip_seip")
 138         self.ueip = Signal(name="mip_uiep")
 139         self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts
 140         self.stip = Signal(name="mip_stip")
 141         self.msip = Signal(name="mip_stip")
 142         self.utip = Signal(name="mip_utip")
 143         self.ssip = Signal(name="mip_ssip")
 144         self.usip = Signal(name="mip_usip")
 145
 146         for n in dir(self):
 147             if n in ['make', 'comb', 'sync'] or n.startswith("_"):
 148                 continue
 149             self.comb += getattr(self, n).eq(0x0)
 150
 151     def make(self):
 152         return Cat( self.usip, self.ssip, 0, self.msip,
 153                     self.utip, self.stip, 0, self.mtip,
 154                     self.ueip, self.seip, 0, self.meip, )
 155
 156
 157 class M:
 158     def __init__(self, comb, sync):
 159         self.comb = comb
 160         self.sync = sync
 161         self.mcause = Signal(32)
 162         self.mepc = Signal(32)
 163         self.mscratch = Signal(32)
 164         self.sync += self.mcause.eq(0)
 165         self.sync += self.mepc.eq(0) # 32'hXXXXXXXX;
 166         self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
 167
 168
 169 class Misa:
 170     def __init__(self, comb, sync):
 171         self.comb = comb
 172         self.sync = sync
 173         self.misa = Signal(32)
 174         cl = []
 175         for l in list(string.ascii_lowercase):
 176             value = 1 if l == 'i' else 0
 177             cl.append(Constant(value))
 178         cl.append(Constant(0, 4))
 179         cl.append(Constant(0b01, 2))
 180         self.comb += self.misa.eq(Cat(cl))
 181
 182
 183 class Fetch:
 184     def __init__(self, comb, sync):
 185         self.comb = comb
 186         self.sync = sync
 187         self.action = Signal(fetch_action, name="fetch_action")
 188         self.target_pc = Signal(32, name="fetch_target_pc")
 189         self.output_pc = Signal(32, name="fetch_output_pc")
 190         self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
 191         self.output_state = Signal(fetch_output_state,name="fetch_output_state")
 192
 193     def get_fetch_action(self, dc, load_store_misaligned, mi,
 194                          branch_taken, misaligned_jump_target,
 195                          csr_op_is_valid):
 196         c = {}
 197         c["default"] = self.action.eq(FA.default) # XXX should be 32'XXXXXXXX?
 198         c[FOS.empty] = self.action.eq(FA.default)
 199         c[FOS.trap] = self.action.eq(FA.ack_trap)
 200
 201         # illegal instruction -> error trap
 202         i= If((dc.act & DA.trap_illegal_instruction) != 0,
 203                  self.action.eq(FA.error_trap)
 204               )
 205
 206         # ecall / ebreak -> noerror trap
 207         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
 208                  self.action.eq(FA.noerror_trap))
 209
 210         # load/store: check alignment, check wait
 211         i = i.Elif((dc.act & (DA.load | DA.store)) != 0,
 212                 If((load_store_misaligned | ~mi.rw_address_valid),
 213                     self.action.eq(FA.error_trap) # misaligned or invalid addr
 214                 ).Elif(mi.rw_wait,
 215                     self.action.eq(FA.wait) # wait
 216                 ).Else(
 217                     self.action.eq(FA.default) # ok
 218                 )
 219               )
 220
 221         # fence
 222         i = i.Elif((dc.act & DA.fence) != 0,
 223                  self.action.eq(FA.fence))
 224
 225         # branch -> misaligned=error, otherwise jump
 226         i = i.Elif((dc.act & DA.branch) != 0,
 227                 If(branch_taken,
 228                     If(misaligned_jump_target,
 229                         self.action.eq(FA.error_trap)
 230                     ).Else(
 231                         self.action.eq(FA.jump)
 232                     )
 233                  ).Else(
 234                         self.action.eq(FA.default)
 235                  )
 236               )
 237
 238         # jal/jalr -> misaligned=error, otherwise jump
 239         i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
 240                 If(misaligned_jump_target,
 241                     self.action.eq(FA.error_trap)
 242                 ).Else(
 243                     self.action.eq(FA.jump)
 244                 )
 245               )
 246
 247         # csr -> opvalid=ok, else error trap
 248         i = i.Elif((dc.act & DA.csr) != 0,
 249                 If(csr_op_is_valid,
 250                     self.action.eq(FA.default)
 251                 ).Else(
 252                     self.action.eq(FA.error_trap)
 253                 )
 254               )
 255
 256         c[FOS.valid] = i
 257
 258         return Case(self.output_state, c)
 259
 260 class CSR:
 261     def __init__(self, comb, sync, dc, register_rs1):
 262         self.comb = comb
 263         self.sync = sync
 264         self.number = Signal(12, name="csr_number")
 265         self.input_value = Signal(32, name="csr_input_value")
 266         self.reads = Signal(name="csr_reads")
 267         self.writes = Signal(name="csr_writes")
 268         self.op_is_valid = Signal(name="csr_op_is_valid")
 269
 270         self.comb += self.number.eq(dc.immediate)
 271         self.comb += self.input_value.eq(Mux(dc.funct3[2],
 272                                             dc.rs1,
 273                                             register_rs1))
 274         self.comb += self.reads.eq(dc.funct3[1] | (dc.rd != 0))
 275         self.comb += self.writes.eq(~dc.funct3[1] | (dc.rs1 != 0))
 276
 277         self.comb += self.get_csr_op_is_valid()
 278
 279     def get_csr_op_is_valid(self):
 280         """ determines if a CSR is valid
 281         """
 282         c = {}
 283         # invalid csrs
 284         for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr,
 285                   csr_uie, csr_utvec, csr_uscratch, csr_uepc,
 286                   csr_ucause, csr_utval, csr_uip, csr_sstatus,
 287                   csr_sedeleg, csr_sideleg, csr_sie, csr_stvec,
 288                   csr_scounteren, csr_sscratch, csr_sepc, csr_scause,
 289                   csr_stval, csr_sip, csr_satp, csr_medeleg,
 290                   csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]:
 291             c[f] = self.op_is_valid.eq(0)
 292
 293         # not-writeable -> ok
 294         for f in [csr_cycle, csr_time, csr_instret, csr_cycleh,
 295                   csr_timeh, csr_instreth, csr_mvendorid, csr_marchid,
 296                   csr_mimpid, csr_mhartid]:
 297             c[f] = self.op_is_valid.eq(~self.writes)
 298
 299         # valid csrs
 300         for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec,
 301                   csr_mscratch, csr_mepc, csr_mcause, csr_mip]:
 302             c[f] = self.op_is_valid.eq(1)
 303
 304         # not implemented / default
 305         for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret,
 306                   csr_mcycleh, csr_minstreth, "default"]:
 307             c[f] = self.op_is_valid.eq(0)
 308
 309         return Case(self.number, c)
 310
 311     def evaluate_csr_funct3_op(self, funct3, previous, written):
 312         c = { "default": written.eq(Constant(0, 32))}
 313         for f in [F3.csrrw, F3.csrrwi]:
 314             c[f] = written.eq(self.input_value)
 315         for f in [F3.csrrs, F3.csrrsi]:
 316             c[f] = written.eq(self.input_value | previous)
 317         for f in [F3.csrrc, F3.csrrci]:
 318             c[f] = written.eq(~self.input_value & previous)
 319         return Case(funct3, c)
 320
 321
 322 class MInfo:
 323     def __init__(self, comb):
 324         self.comb = comb
 325         # TODO
 326         self.cycle_counter   = Signal(64); # TODO: implement cycle_counter
 327         self.time_counter    = Signal(64); # TODO: implement time_counter
 328         self.instret_counter = Signal(64); # TODO: implement instret_counter
 329
 330         self.mvendorid = Signal(32)
 331         self.marchid = Signal(32)
 332         self.mimpid = Signal(32)
 333         self.mhartid = Signal(32)
 334         self.comb += self.mvendorid.eq(Constant(0, 32))
 335         self.comb += self.marchid.eq(Constant(0, 32))
 336         self.comb += self.mimpid.eq(Constant(0, 32))
 337         self.comb += self.mhartid.eq(Constant(0, 32))
 338
 339 class Regs:
 340     def __init__(self, comb, sync):
 341         self.comb = comb
 342         self.sync = sync
 343
 344         self.ra_en = Signal(reset=1, name="regfile_ra_en") # TODO: ondemand en
 345         self.rs1 = Signal(32, name="regfile_rs1")
 346         self.rs_a = Signal(5, name="regfile_rs_a")
 347
 348         self.rb_en = Signal(reset=1, name="regfile_rb_en") # TODO: ondemand en
 349         self.rs2 = Signal(32, name="regfile_rs2")
 350         self.rs_b = Signal(5, name="regfile_rs_b")
 351
 352         self.w_en = Signal(name="regfile_w_en")
 353         self.wval = Signal(32, name="regfile_wval")
 354         self.rd = Signal(32, name="regfile_rd")
 355
 356 class CPU(Module):
 357     """
 358     """
 359
 360     def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
 361         """ returns whether a load/store is misaligned
 362         """
 363         return Case(funct3[:2],
 364                 { F3.sb: ls.eq(Constant(0)),
 365                   F3.sh: ls.eq(load_store_address_low_2[0] != 0),
 366                   F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
 367                   "default": ls.eq(Constant(1))
 368                 })
 369
 370     def get_lsbm(self, dc):
 371         return Cat(Constant(1),
 372                    Mux((dc.funct3[1] | dc.funct3[0]),
 373                        Constant(1), Constant(0)),
 374                    Mux((dc.funct3[1]),
 375                        Constant(0b11, 2), Constant(0, 2)))
 376
 377     # XXX this happens to get done by various self.sync actions
 378     #def reset_to_initial(self, m, mstatus, mie, registers):
 379     #    return [m.mcause.eq(0),
 380     #            ]
 381
 382     def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
 383         s = [ms.mpie.eq(ms.mie),
 384              ms.mie.eq(0),
 385              m.mepc.eq(Mux(ft.action == FA.noerror_trap,
 386                            ft.output_pc + 4,
 387                            ft.output_pc))]
 388
 389         # fetch action ack trap
 390         i = If(ft.action == FA.ack_trap,
 391                 m.mcause.eq(cause_instruction_access_fault)
 392               )
 393
 394         # ecall/ebreak
 395         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
 396                 m.mcause.eq(Mux(dc.immediate[0],
 397                                 cause_machine_environment_call,
 398                                 cause_breakpoint))
 399               )
 400
 401         # load
 402         i = i.Elif((dc.act & DA.load) != 0,
 403                 If(load_store_misaligned,
 404                     m.mcause.eq(cause_load_address_misaligned)
 405                 ).Else(
 406                     m.mcause.eq(cause_load_access_fault)
 407                 )
 408               )
 409
 410         # store
 411         i = i.Elif((dc.act & DA.store) != 0,
 412                 If(load_store_misaligned,
 413                     m.mcause.eq(cause_store_amo_address_misaligned)
 414                 ).Else(
 415                     m.mcause.eq(cause_store_amo_access_fault)
 416                 )
 417               )
 418
 419         # jal/jalr -> misaligned=error, otherwise jump
 420         i = i.Elif((dc.act & (DA.jal | DA.jalr | DA.branch)) != 0,
 421                 m.mcause.eq(cause_instruction_address_misaligned)
 422               )
 423
 424         # defaults to illegal instruction
 425         i = i.Else(m.mcause.eq(cause_illegal_instruction))
 426
 427         s.append(i)
 428         return s
 429
 430     def main_block(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
 431                          ft, dc,
 432                          load_store_misaligned,
 433                          loaded_value, alu_result,
 434                          lui_auipc_result):
 435         c = {}
 436         c[FOS.empty] = []
 437         c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc,
 438                                        load_store_misaligned)
 439         c[FOS.valid] = self.handle_valid(mtvec, mip, minfo, misa, csr, mi, m,
 440                                        mstatus, mie, ft, dc,
 441                                        load_store_misaligned,
 442                                        loaded_value,
 443                                        alu_result,
 444                                        lui_auipc_result)
 445         return Case(ft.output_state, c)
 446
 447     def write_register(self, rd, val):
 448         return [self.regs.rd.eq(rd),
 449                 self.regs.wval.eq(val),
 450                 self.regs.w_en.eq(1)
 451                ]
 452
 453     def handle_valid(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
 454                            ft, dc,
 455                            load_store_misaligned,
 456                            loaded_value, alu_result,
 457                            lui_auipc_result):
 458         # fetch action ack trap
 459         i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
 460                 [self.handle_trap(m, mstatus, ft, dc,
 461                                        load_store_misaligned),
 462                  self.regs.w_en.eq(0) # no writing to registers
 463                 ]
 464               )
 465
 466         # load
 467         i = i.Elif((dc.act & DA.load) != 0,
 468                 If(~mi.rw_wait,
 469                     self.write_register(dc.rd, loaded_value)
 470                 )
 471               )
 472
 473         # op or op_immediate
 474         i = i.Elif((dc.act & DA.op_op_imm) != 0,
 475                 self.write_register(dc.rd, alu_result)
 476               )
 477
 478         # lui or auipc
 479         i = i.Elif((dc.act & DA.lui_auipc) != 0,
 480                 self.write_register(dc.rd, lui_auipc_result)
 481               )
 482
 483         # jal/jalr
 484         i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
 485                 self.write_register(dc.rd, ft.output_pc + 4)
 486               )
 487
 488         i = i.Elif((dc.act & DA.csr) != 0,
 489                 self.handle_csr(mtvec, mip, minfo, misa, mstatus, mie, m,
 490                                 dc, csr)
 491               )
 492
 493         # fence, store, branch
 494         i = i.Elif((dc.act & (DA.fence | DA.fence_i |
 495                               DA.store | DA.branch)) != 0,
 496                 # do nothing
 497                self.regs.w_en.eq(0) # no writing to registers
 498               )
 499
 500         return i
 501
 502     def handle_csr(self, mtvec, mip, minfo, misa, mstatus, mie, m, dc, csr):
 503         csr_output_value = Signal(32)
 504         csr_written_value = Signal(32)
 505         c = {}
 506
 507         # cycle
 508         c[csr_cycle]  = csr_output_value.eq(minfo.cycle_counter[0:32])
 509         c[csr_cycleh] = csr_output_value.eq(minfo.cycle_counter[32:64])
 510         # time
 511         c[csr_time]  = csr_output_value.eq(minfo.time_counter[0:32])
 512         c[csr_timeh] = csr_output_value.eq(minfo.time_counter[32:64])
 513         # instret
 514         c[csr_instret]  = csr_output_value.eq(minfo.instret_counter[0:32])
 515         c[csr_instreth] = csr_output_value.eq(minfo.instret_counter[32:64])
 516         # mvendorid/march/mimpl/mhart
 517         c[csr_mvendorid] = csr_output_value.eq(minfo.mvendorid)
 518         c[csr_marchid  ] = csr_output_value.eq(minfo.marchid  )
 519         c[csr_mimpid   ] = csr_output_value.eq(minfo.mimpid   )
 520         c[csr_mhartid  ] = csr_output_value.eq(minfo.mhartid  )
 521         # misa
 522         c[csr_misa     ] = csr_output_value.eq(misa.misa)
 523         # mstatus
 524         c[csr_mstatus  ] = [
 525             csr_output_value.eq(mstatus.make()),
 526             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 527                                                   csr_written_value),
 528             mstatus.mpie.eq(csr_written_value[7]),
 529             mstatus.mie.eq(csr_written_value[3])
 530         ]
 531         # mie
 532         c[csr_mie      ] = [
 533             csr_output_value.eq(mie.make()),
 534             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 535                                                   csr_written_value),
 536             mie.meie.eq(csr_written_value[11]),
 537             mie.mtie.eq(csr_written_value[7]),
 538             mie.msie.eq(csr_written_value[3]),
 539         ]
 540         # mtvec
 541         c[csr_mtvec    ] = csr_output_value.eq(mtvec)
 542         # mscratch
 543         c[csr_mscratch ] = [
 544             csr_output_value.eq(m.mscratch),
 545             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 546                                                   csr_written_value),
 547             If(csr.writes,
 548                 m.mscratch.eq(csr_written_value),
 549             )
 550         ]
 551         # mepc
 552         c[csr_mepc ] = [
 553             csr_output_value.eq(m.mepc),
 554             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 555                                                   csr_written_value),
 556             If(csr.writes,
 557                 m.mepc.eq(csr_written_value),
 558             )
 559         ]
 560
 561         # mcause
 562         c[csr_mcause ] = [
 563             csr_output_value.eq(m.mcause),
 564             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 565                                                   csr_written_value),
 566             If(csr.writes,
 567                 m.mcause.eq(csr_written_value),
 568             )
 569         ]
 570
 571         # mip
 572         c[csr_mip  ] = [
 573             csr_output_value.eq(mip.make()),
 574             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 575                                                   csr_written_value),
 576         ]
 577
 578         return [Case(csr.number, c),
 579                 If(csr.reads,
 580                     self.write_register(dc.rd, csr_output_value)
 581                 )]
 582
 583         """
 584                 `csr_mip: begin
 585                     csr_output_value = 0;
 586                     csr_output_value[11] = mip_meip;
 587                     csr_output_value[9] = mip_seip;
 588                     csr_output_value[8] = mip_ueip;
 589                     csr_output_value[7] = mip_mtip;
 590                     csr_output_value[5] = mip_stip;
 591                     csr_output_value[4] = mip_utip;
 592                     csr_output_value[3] = mip_msip;
 593                     csr_output_value[1] = mip_ssip;
 594                     csr_output_value[0] = mip_usip;
 595                 end
 596                 endcase
 597         end
 598         endcase
 599     end
 600         """
 601     def __init__(self):
 602         Module.__init__(self)
 603         self.clk = ClockSignal()
 604         self.reset = ResetSignal()
 605         self.tty_write = Signal()
 606         self.tty_write_data = Signal(8)
 607         self.tty_write_busy = Signal()
 608         self.switch_2 = Signal()
 609         self.switch_3 = Signal()
 610         self.led_1 = Signal()
 611         self.led_3 = Signal()
 612
 613         ram_size = Constant(0x8000)
 614         ram_start = Constant(0x10000, 32)
 615         reset_vector = Signal(32)
 616         mtvec = Signal(32)
 617
 618         reset_vector.eq(ram_start)
 619         mtvec.eq(ram_start + 0x40)
 620
 621         self.regs = Regs(self.comb, self.sync)
 622
 623         rf = Instance("RegFile", name="regfile",
 624            i_ra_en = self.regs.ra_en,
 625            i_rb_en = self.regs.rb_en,
 626            i_w_en = self.regs.w_en,
 627            o_read_a = self.regs.rs1,
 628            o_read_b = self.regs.rs2,
 629            i_writeval = self.regs.wval,
 630            i_rs_a = self.regs.rs_a,
 631            i_rs_b = self.regs.rs_b,
 632            i_rd = self.regs.rd)
 633
 634         self.specials += rf
 635
 636         mi = MemoryInterface()
 637
 638         mii = Instance("cpu_memory_interface", name="memory_instance",
 639                     p_ram_size = ram_size,
 640                     p_ram_start = ram_start,
 641                     i_clk=ClockSignal(),
 642                     i_rst=ResetSignal(),
 643                     i_fetch_address = mi.fetch_address,
 644                     o_fetch_data = mi.fetch_data,
 645                     o_fetch_valid = mi.fetch_valid,
 646                     i_rw_address = mi.rw_address,
 647                     i_rw_byte_mask = mi.rw_byte_mask,
 648                     i_rw_read_not_write = mi.rw_read_not_write,
 649                     i_rw_active = mi.rw_active,
 650                     i_rw_data_in = mi.rw_data_in,
 651                     o_rw_data_out = mi.rw_data_out,
 652                     o_rw_address_valid = mi.rw_address_valid,
 653                     o_rw_wait = mi.rw_wait,
 654                     o_tty_write = self.tty_write,
 655                     o_tty_write_data = self.tty_write_data,
 656                     i_tty_write_busy = self.tty_write_busy,
 657                     i_switch_2 = self.switch_2,
 658                     i_switch_3 = self.switch_3,
 659                     o_led_1 = self.led_1,
 660                     o_led_3 = self.led_3
 661                   )
 662         self.specials += mii
 663
 664         ft = Fetch(self.comb, self.sync)
 665
 666         fs = Instance("CPUFetchStage", name="fetch_stage",
 667             i_clk=ClockSignal(),
 668             i_rst=ResetSignal(),
 669             o_memory_interface_fetch_address = mi.fetch_address,
 670             i_memory_interface_fetch_data = mi.fetch_data,
 671             i_memory_interface_fetch_valid = mi.fetch_valid,
 672             i_fetch_action = ft.action,
 673             i_target_pc = ft.target_pc,
 674             o_output_pc = ft.output_pc,
 675             o_output_instruction = ft.output_instruction,
 676             o_output_state = ft.output_state,
 677             i_reset_vector = reset_vector,
 678             i_mtvec = mtvec,
 679         )
 680         self.specials += fs
 681
 682         dc = Decoder()
 683
 684         cd = Instance("CPUDecoder", name="decoder",
 685             i_instruction = ft.output_instruction,
 686             o_funct7 = dc.funct7,
 687             o_funct3 = dc.funct3,
 688             o_rd = dc.rd,
 689             o_rs1 = dc.rs1,
 690             o_rs2 = dc.rs2,
 691             o_immediate = dc.immediate,
 692             o_opcode = dc.opcode,
 693             o_decode_action = dc.act
 694         )
 695         self.specials += cd
 696
 697         self.comb += self.regs.rs_a.eq(dc.rs1)
 698         self.comb += self.regs.rs_b.eq(dc.rs2)
 699
 700         load_store_address = Signal(32)
 701         load_store_address_low_2 = Signal(2)
 702
 703         self.comb += load_store_address.eq(dc.immediate + self.regs.rs1)
 704         self.comb += load_store_address_low_2.eq(
 705                             dc.immediate[:2] + self.regs.rs1[:2])
 706
 707         load_store_misaligned = Signal()
 708
 709         lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3,
 710                                      load_store_address_low_2)
 711         self.comb += lsa
 712
 713         # XXX rwaddr not 31:2 any more
 714         self.comb += mi.rw_address.eq(load_store_address[2:])
 715
 716         unshifted_load_store_byte_mask = Signal(4)
 717
 718         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc))
 719
 720         # XXX yuck.  this will cause migen simulation to fail
 721         # (however conversion to verilog works)
 722         self.comb += mi.rw_byte_mask.eq(
 723                 _Operator("<<", [unshifted_load_store_byte_mask,
 724                                         load_store_address_low_2]))
 725
 726         # XXX not obvious
 727         b3 = Mux(load_store_address_low_2[1],
 728                  Mux(load_store_address_low_2[0], self.regs.rs2[0:8],
 729                                                   self.regs.rs2[8:16]),
 730                  Mux(load_store_address_low_2[0], self.regs.rs2[16:24],
 731                                                   self.regs.rs2[24:32]))
 732         b2 = Mux(load_store_address_low_2[1], self.regs.rs2[0:8],
 733                                               self.regs.rs2[16:24])
 734         b1 = Mux(load_store_address_low_2[0], self.regs.rs2[0:8],
 735                                               self.regs.rs2[8:16])
 736         b0 = self.regs.rs2[0:8]
 737
 738         self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
 739
 740         # XXX not obvious
 741         unmasked_loaded_value = Signal(32)
 742
 743         b0 = Mux(load_store_address_low_2[1],
 744                  Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
 745                                                   mi.rw_data_out[16:24]),
 746                  Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
 747                                                   mi.rw_data_out[0:8]))
 748         b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
 749                                               mi.rw_data_out[8:16])
 750         b23 = mi.rw_data_out[16:32]
 751
 752         self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
 753
 754         # XXX not obvious
 755         loaded_value = Signal(32)
 756
 757         b0 = unmasked_loaded_value[0:8]
 758         b1 = Mux(dc.funct3[0:2] == 0,
 759                 Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8),
 760                 unmasked_loaded_value[8:16])
 761         b2 = Mux(dc.funct3[1] == 0,
 762                 Replicate(~dc.funct3[2] &
 763                            Mux(dc.funct3[0], unmasked_loaded_value[15],
 764                                                   unmasked_loaded_value[7]),
 765                           16),
 766                 unmasked_loaded_value[16:32])
 767
 768         self.comb += loaded_value.eq(Cat(b0, b1, b2))
 769
 770         self.comb += mi.rw_active.eq(~self.reset
 771                         & (ft.output_state == FOS.valid)
 772                         & ~load_store_misaligned
 773                         & ((dc.act & (DA.load | DA.store)) != 0))
 774
 775         self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
 776
 777         # alu
 778         alu_a = Signal(32)
 779         alu_b = Signal(32)
 780         alu_result = Signal(32)
 781
 782         self.comb += alu_a.eq(self.regs.rs1)
 783         self.comb += alu_b.eq(Mux(dc.opcode[5],
 784                                   self.regs.rs2,
 785                                   dc.immediate))
 786
 787         ali = Instance("cpu_alu", name="alu",
 788             i_funct7 = dc.funct7,
 789             i_funct3 = dc.funct3,
 790             i_opcode = dc.opcode,
 791             i_a = alu_a,
 792             i_b = alu_b,
 793             o_result = alu_result
 794         )
 795         self.specials += ali
 796
 797         lui_auipc_result = Signal(32)
 798         self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
 799                                              dc.immediate,
 800                                              dc.immediate + ft.output_pc))
 801
 802         self.comb += ft.target_pc.eq(Cat(0,
 803                     Mux(dc.opcode != OP.jalr,
 804                                 ft.output_pc[1:32],
 805                                 self.regs.rs1[1:32] + dc.immediate[1:32])))
 806
 807         misaligned_jump_target = Signal()
 808         self.comb += misaligned_jump_target.eq(ft.target_pc[1])
 809
 810         branch_arg_a = Signal(32)
 811         branch_arg_b = Signal(32)
 812         self.comb += branch_arg_a.eq(Cat( self.regs.rs1[0:31],
 813                                           self.regs.rs1[31] ^ ~dc.funct3[1]))
 814         self.comb += branch_arg_b.eq(Cat( self.regs.rs2[0:31],
 815                                           self.regs.rs2[31] ^ ~dc.funct3[1]))
 816
 817         branch_taken = Signal()
 818         self.comb += branch_taken.eq(dc.funct3[0] ^
 819                                      Mux(dc.funct3[2],
 820                                          branch_arg_a < branch_arg_b,
 821                                          branch_arg_a == branch_arg_b))
 822
 823         m = M(self.comb, self.sync)
 824         mstatus = MStatus(self.comb, self.sync)
 825         mie = MIE(self.comb, self.sync)
 826         misa = Misa(self.comb, self.sync)
 827         mip = MIP(self.comb, self.sync)
 828
 829         # CSR decoding
 830         csr = CSR(self.comb, self.sync, dc, self.regs.rs1)
 831
 832         self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi,
 833                                  branch_taken, misaligned_jump_target,
 834                                  csr.op_is_valid)
 835
 836         minfo = MInfo(self.comb)
 837
 838         self.sync += If(~self.reset,
 839                         self.main_block(mtvec, mip, minfo, misa, csr, mi, m,
 840                                         mstatus, mie, ft, dc,
 841                                         load_store_misaligned,
 842                                         loaded_value,
 843                                        alu_result,
 844                                        lui_auipc_result)
 845                      )
 846
 847 if __name__ == "__main__":
 848     example = CPU()
 849     print(verilog.convert(example,
 850          {
 851            example.tty_write,
 852            example.tty_write_data,
 853            example.tty_write_busy,
 854            example.switch_2,
 855            example.switch_3,
 856            example.led_1,
 857            example.led_3,
 858            }))