cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 import string
  30 from migen import *
  31 from migen.fhdl import verilog
  32 from migen.fhdl.structure import _Operator
  33
  34 from riscvdefs import *
  35 from cpudefs import *
  36
  37 class MemoryInterface:
  38     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  39     fetch_data = Signal(32, name="memory_interface_fetch_data")
  40     fetch_valid = Signal(name="memory_interface_fetch_valid")
  41     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  42     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  43     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  44     rw_active = Signal(name="memory_interface_rw_active")
  45     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  46     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  47     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  48     rw_wait = Signal(name="memory_interface_rw_wait")
  49
  50
  51 class Decoder:
  52     funct7 = Signal(7, name="decoder_funct7")
  53     funct3 = Signal(3, name="decoder_funct3")
  54     rd = Signal(5, name="decoder_rd")
  55     rs1 = Signal(5, name="decoder_rs1")
  56     rs2 = Signal(5, name="decoder_rs2")
  57     immediate = Signal(32, name="decoder_immediate")
  58     opcode = Signal(7, name="decoder_opcode")
  59     act = Signal(decode_action, name="decoder_action")
  60
  61
  62 class MStatus:
  63     def __init__(self, comb, sync):
  64         self.comb = comb
  65         self.sync = sync
  66         self.mpie = Signal(name="mstatus_mpie")
  67         self.mie = Signal(name="mstatus_mie")
  68         self.mstatus = Signal(32, name="mstatus")
  69
  70         self.sync += self.mie.eq(0)
  71         self.sync += self.mpie.eq(0)
  72         self.sync += self.mstatus.eq(0)
  73
  74
  75 class MIE:
  76     def __init__(self, comb, sync):
  77         self.comb = comb
  78         self.sync = sync
  79         self.meie = Signal(name="mie_meie")
  80         self.mtie = Signal(name="mie_mtie")
  81         self.msie = Signal(name="mie_msie")
  82         self.mie = Signal(32)
  83
  84
  85 class MIP:
  86     def __init__(self):
  87         self.mip = Signal(32)
  88
  89
  90 class M:
  91     def __init__(self, comb, sync):
  92         self.comb = comb
  93         self.sync = sync
  94         self.mcause = Signal(32)
  95         self.mepc = Signal(32)
  96         self.mscratch = Signal(32)
  97         self.sync += self.mcause.eq(0)
  98         self.sync += self.mepc.eq(0) # 32'hXXXXXXXX;
  99         self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
 100
 101
 102 class Misa:
 103     def __init__(self, comb, sync):
 104         self.comb = comb
 105         self.sync = sync
 106         self.misa = Signal(32)
 107         cl = []
 108         for l in list(string.ascii_lowercase):
 109             value = 1 if l == 'i' else 0
 110             cl.append(Constant(value))
 111         cl.append(Constant(0, 4))
 112         cl.append(Constant(0b01, 2))
 113         self.comb += self.misa.eq(Cat(cl))
 114
 115
 116 class Fetch:
 117     def __init__(self, comb, sync):
 118         self.comb = comb
 119         self.sync = sync
 120         self.action = Signal(fetch_action, name="fetch_action")
 121         self.target_pc = Signal(32, name="fetch_target_pc")
 122         self.output_pc = Signal(32, name="fetch_output_pc")
 123         self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
 124         self.output_state = Signal(fetch_output_state,name="fetch_output_state")
 125
 126 class CSR:
 127     def __init__(self, comb, sync, dc, register_rs1):
 128         self.comb = comb
 129         self.sync = sync
 130         self.number = Signal(12, name="csr_number")
 131         self.input_value = Signal(32, name="csr_input_value")
 132         self.reads = Signal(name="csr_reads")
 133         self.writes = Signal(name="csr_writes")
 134         self.op_is_valid = Signal(name="csr_op_is_valid")
 135
 136         self.comb += self.number.eq(dc.immediate)
 137         self.comb += self.input_value.eq(Mux(dc.funct3[2],
 138                                             dc.rs1,
 139                                             register_rs1))
 140         self.comb += self.reads.eq(dc.funct3[1] | (dc.rd != 0))
 141         self.comb += self.writes.eq(~dc.funct3[1] | (dc.rs1 != 0))
 142
 143         self.comb += self.get_csr_op_is_valid()
 144
 145     def get_csr_op_is_valid(self):
 146         """ determines if a CSR is valid
 147         """
 148         c = {}
 149         # invalid csrs
 150         for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr,
 151                   csr_uie, csr_utvec, csr_uscratch, csr_uepc,
 152                   csr_ucause, csr_utval, csr_uip, csr_sstatus,
 153                   csr_sedeleg, csr_sideleg, csr_sie, csr_stvec,
 154                   csr_scounteren, csr_sscratch, csr_sepc, csr_scause,
 155                   csr_stval, csr_sip, csr_satp, csr_medeleg,
 156                   csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]:
 157             c[f] = self.op_is_valid.eq(0)
 158
 159         # not-writeable -> ok
 160         for f in [csr_cycle, csr_time, csr_instret, csr_cycleh,
 161                   csr_timeh, csr_instreth, csr_mvendorid, csr_marchid,
 162                   csr_mimpid, csr_mhartid]:
 163             c[f] = self.op_is_valid.eq(~self.writes)
 164
 165         # valid csrs
 166         for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec,
 167                   csr_mscratch, csr_mepc, csr_mcause, csr_mip]:
 168             c[f] = self.op_is_valid.eq(1)
 169
 170         # not implemented / default
 171         for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret,
 172                   csr_mcycleh, csr_minstreth, "default"]:
 173             c[f] = self.op_is_valid.eq(0)
 174
 175         return Case(self.number, c)
 176
 177     def evaluate_csr_funct3_op(self, funct3, previous, written):
 178         c = { "default": written.eq(Constant(0, 32))}
 179         for f in [F3.csrrw, F3.csrrwi]:
 180             c[f] = written.eq(self.input_value)
 181         for f in [F3.csrrs, F3.csrrsi]:
 182             c[f] = written.eq(self.input_value | previous)
 183         for f in [F3.csrrc, F3.csrrci]:
 184             c[f] = written.eq(~self.input_value & previous)
 185         return Case(funct3, c)
 186
 187
 188 class MInfo:
 189     def __init__(self, comb):
 190         self.comb = comb
 191         # TODO
 192         self.cycle_counter   = Signal(64); # TODO: implement cycle_counter
 193         self.time_counter    = Signal(64); # TODO: implement time_counter
 194         self.instret_counter = Signal(64); # TODO: implement instret_counter
 195
 196         self.mvendorid = Signal(32)
 197         self.marchid = Signal(32)
 198         self.mimpid = Signal(32)
 199         self.mhartid = Signal(32)
 200         self.comb += self.mvendorid.eq(Constant(0, 32))
 201         self.comb += self.marchid.eq(Constant(0, 32))
 202         self.comb += self.mimpid.eq(Constant(0, 32))
 203         self.comb += self.mhartid.eq(Constant(0, 32))
 204
 205 class Regs:
 206     def __init__(self, comb, sync):
 207         self.comb = comb
 208         self.sync = sync
 209
 210         self.ra_en = Signal(reset=1, name="regfile_ra_en") # TODO: ondemand en
 211         self.rs1 = Signal(32, name="regfile_rs1")
 212         self.rs_a = Signal(5, name="regfile_rs_a")
 213
 214         self.rb_en = Signal(reset=1, name="regfile_rb_en") # TODO: ondemand en
 215         self.rs2 = Signal(32, name="regfile_rs2")
 216         self.rs_b = Signal(5, name="regfile_rs_b")
 217
 218         self.w_en = Signal(name="regfile_w_en")
 219         self.wval = Signal(32, name="regfile_wval")
 220         self.rd = Signal(32, name="regfile_rd")
 221
 222 class CPU(Module):
 223     """
 224     """
 225
 226     def get_lsbm(self, dc):
 227         return Cat(Constant(1),
 228                    Mux((dc.funct3[1] | dc.funct3[0]),
 229                        Constant(1), Constant(0)),
 230                    Mux((dc.funct3[1]),
 231                        Constant(0b11, 2), Constant(0, 2)))
 232
 233     # XXX this happens to get done by various self.sync actions
 234     #def reset_to_initial(self, m, mstatus, mie, registers):
 235     #    return [m.mcause.eq(0),
 236     #            ]
 237
 238     def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
 239         s = [ms.mpie.eq(ms.mie),
 240              ms.mie.eq(0),
 241              m.mepc.eq(Mux(ft.action == FA.noerror_trap,
 242                            ft.output_pc + 4,
 243                            ft.output_pc))]
 244
 245         # fetch action ack trap
 246         i = If(ft.action == FA.ack_trap,
 247                 m.mcause.eq(cause_instruction_access_fault)
 248               )
 249
 250         # ecall/ebreak
 251         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
 252                 m.mcause.eq(Mux(dc.immediate[0],
 253                                 cause_machine_environment_call,
 254                                 cause_breakpoint))
 255               )
 256
 257         # load
 258         i = i.Elif((dc.act & DA.load) != 0,
 259                 If(load_store_misaligned,
 260                     m.mcause.eq(cause_load_address_misaligned)
 261                 ).Else(
 262                     m.mcause.eq(cause_load_access_fault)
 263                 )
 264               )
 265
 266         # store
 267         i = i.Elif((dc.act & DA.store) != 0,
 268                 If(load_store_misaligned,
 269                     m.mcause.eq(cause_store_amo_address_misaligned)
 270                 ).Else(
 271                     m.mcause.eq(cause_store_amo_access_fault)
 272                 )
 273               )
 274
 275         # jal/jalr -> misaligned=error, otherwise jump
 276         i = i.Elif((dc.act & (DA.jal | DA.jalr | DA.branch)) != 0,
 277                 m.mcause.eq(cause_instruction_address_misaligned)
 278               )
 279
 280         # defaults to illegal instruction
 281         i = i.Else(m.mcause.eq(cause_illegal_instruction))
 282
 283         s.append(i)
 284         return s
 285
 286     def main_block(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
 287                          ft, dc,
 288                          load_store_misaligned,
 289                          loaded_value, alu_result,
 290                          lui_auipc_result):
 291         c = {}
 292         c[FOS.empty] = []
 293         c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc,
 294                                        load_store_misaligned)
 295         c[FOS.valid] = self.handle_valid(mtvec, mip, minfo, misa, csr, mi, m,
 296                                        mstatus, mie, ft, dc,
 297                                        load_store_misaligned,
 298                                        loaded_value,
 299                                        alu_result,
 300                                        lui_auipc_result)
 301         return Case(ft.output_state, c)
 302
 303     def write_register(self, rd, val):
 304         return [self.regs.rd.eq(rd),
 305                 self.regs.wval.eq(val),
 306                 self.regs.w_en.eq(1)
 307                ]
 308
 309     def handle_valid(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
 310                            ft, dc,
 311                            load_store_misaligned,
 312                            loaded_value, alu_result,
 313                            lui_auipc_result):
 314         # fetch action ack trap
 315         i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
 316                 [self.handle_trap(m, mstatus, ft, dc,
 317                                        load_store_misaligned),
 318                  self.regs.w_en.eq(0) # no writing to registers
 319                 ]
 320               )
 321
 322         # load
 323         i = i.Elif((dc.act & DA.load) != 0,
 324                 If(~mi.rw_wait,
 325                     self.write_register(dc.rd, loaded_value)
 326                 )
 327               )
 328
 329         # op or op_immediate
 330         i = i.Elif((dc.act & DA.op_op_imm) != 0,
 331                 self.write_register(dc.rd, alu_result)
 332               )
 333
 334         # lui or auipc
 335         i = i.Elif((dc.act & DA.lui_auipc) != 0,
 336                 self.write_register(dc.rd, lui_auipc_result)
 337               )
 338
 339         # jal/jalr
 340         i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
 341                 self.write_register(dc.rd, ft.output_pc + 4)
 342               )
 343
 344         i = i.Elif((dc.act & DA.csr) != 0,
 345                 self.handle_csr(mtvec, mip, minfo, misa, mstatus, mie, m,
 346                                 dc, csr)
 347               )
 348
 349         # fence, store, branch
 350         i = i.Elif((dc.act & (DA.fence | DA.fence_i |
 351                               DA.store | DA.branch)) != 0,
 352                 # do nothing
 353                self.regs.w_en.eq(0) # no writing to registers
 354               )
 355
 356         return i
 357
 358     def handle_csr(self, mtvec, mip, minfo, misa, mstatus, mie, m, dc, csr):
 359         csr_output_value = Signal(32)
 360         csr_written_value = Signal(32)
 361         c = {}
 362
 363         # cycle
 364         c[csr_cycle]  = csr_output_value.eq(minfo.cycle_counter[0:32])
 365         c[csr_cycleh] = csr_output_value.eq(minfo.cycle_counter[32:64])
 366         # time
 367         c[csr_time]  = csr_output_value.eq(minfo.time_counter[0:32])
 368         c[csr_timeh] = csr_output_value.eq(minfo.time_counter[32:64])
 369         # instret
 370         c[csr_instret]  = csr_output_value.eq(minfo.instret_counter[0:32])
 371         c[csr_instreth] = csr_output_value.eq(minfo.instret_counter[32:64])
 372         # mvendorid/march/mimpl/mhart
 373         c[csr_mvendorid] = csr_output_value.eq(minfo.mvendorid)
 374         c[csr_marchid  ] = csr_output_value.eq(minfo.marchid  )
 375         c[csr_mimpid   ] = csr_output_value.eq(minfo.mimpid   )
 376         c[csr_mhartid  ] = csr_output_value.eq(minfo.mhartid  )
 377         # misa
 378         c[csr_misa     ] = csr_output_value.eq(misa.misa)
 379         # mstatus
 380         c[csr_mstatus  ] = [
 381             csr_output_value.eq(mstatus.mstatus),
 382             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 383                                                   csr_written_value),
 384             mstatus.mpie.eq(csr_written_value[7]),
 385             mstatus.mie.eq(csr_written_value[3])
 386         ]
 387         # mie
 388         c[csr_mie      ] = [
 389             csr_output_value.eq(mie.mie),
 390             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 391                                                   csr_written_value),
 392             mie.meie.eq(csr_written_value[11]),
 393             mie.mtie.eq(csr_written_value[7]),
 394             mie.msie.eq(csr_written_value[3]),
 395         ]
 396         # mtvec
 397         c[csr_mtvec    ] = csr_output_value.eq(mtvec)
 398         # mscratch
 399         c[csr_mscratch ] = [
 400             csr_output_value.eq(m.mscratch),
 401             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 402                                                   csr_written_value),
 403             If(csr.writes,
 404                 m.mscratch.eq(csr_written_value),
 405             )
 406         ]
 407         # mepc
 408         c[csr_mepc ] = [
 409             csr_output_value.eq(m.mepc),
 410             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 411                                                   csr_written_value),
 412             If(csr.writes,
 413                 m.mepc.eq(csr_written_value),
 414             )
 415         ]
 416
 417         # mcause
 418         c[csr_mcause ] = [
 419             csr_output_value.eq(m.mcause),
 420             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 421                                                   csr_written_value),
 422             If(csr.writes,
 423                 m.mcause.eq(csr_written_value),
 424             )
 425         ]
 426
 427         # mip
 428         c[csr_mip  ] = [
 429             csr_output_value.eq(mip.mip),
 430             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 431                                                   csr_written_value),
 432         ]
 433
 434         return [Case(csr.number, c),
 435                 If(csr.reads,
 436                     self.write_register(dc.rd, csr_output_value)
 437                 )]
 438
 439     def __init__(self):
 440         Module.__init__(self)
 441         self.clk = ClockSignal()
 442         self.reset = ResetSignal()
 443         self.tty_write = Signal()
 444         self.tty_write_data = Signal(8)
 445         self.tty_write_busy = Signal()
 446         self.switch_2 = Signal()
 447         self.switch_3 = Signal()
 448         self.led_1 = Signal()
 449         self.led_3 = Signal()
 450
 451         ram_size = Constant(0x8000)
 452         ram_start = Constant(0x10000, 32)
 453         reset_vector = Signal(32)
 454         mtvec = Signal(32)
 455
 456         reset_vector.eq(ram_start)
 457         mtvec.eq(ram_start + 0x40)
 458
 459         self.regs = Regs(self.comb, self.sync)
 460
 461         rf = Instance("RegFile", name="regfile",
 462            i_ra_en = self.regs.ra_en,
 463            i_rb_en = self.regs.rb_en,
 464            i_w_en = self.regs.w_en,
 465            o_read_a = self.regs.rs1,
 466            o_read_b = self.regs.rs2,
 467            i_writeval = self.regs.wval,
 468            i_rs_a = self.regs.rs_a,
 469            i_rs_b = self.regs.rs_b,
 470            i_rd = self.regs.rd)
 471
 472         self.specials += rf
 473
 474         mi = MemoryInterface()
 475
 476         mii = Instance("cpu_memory_interface", name="memory_instance",
 477                     p_ram_size = ram_size,
 478                     p_ram_start = ram_start,
 479                     i_clk=ClockSignal(),
 480                     i_rst=ResetSignal(),
 481                     i_fetch_address = mi.fetch_address,
 482                     o_fetch_data = mi.fetch_data,
 483                     o_fetch_valid = mi.fetch_valid,
 484                     i_rw_address = mi.rw_address,
 485                     i_rw_byte_mask = mi.rw_byte_mask,
 486                     i_rw_read_not_write = mi.rw_read_not_write,
 487                     i_rw_active = mi.rw_active,
 488                     i_rw_data_in = mi.rw_data_in,
 489                     o_rw_data_out = mi.rw_data_out,
 490                     o_rw_address_valid = mi.rw_address_valid,
 491                     o_rw_wait = mi.rw_wait,
 492                     o_tty_write = self.tty_write,
 493                     o_tty_write_data = self.tty_write_data,
 494                     i_tty_write_busy = self.tty_write_busy,
 495                     i_switch_2 = self.switch_2,
 496                     i_switch_3 = self.switch_3,
 497                     o_led_1 = self.led_1,
 498                     o_led_3 = self.led_3
 499                   )
 500         self.specials += mii
 501
 502         ft = Fetch(self.comb, self.sync)
 503
 504         fs = Instance("CPUFetchStage", name="fetch_stage",
 505             i_clk=ClockSignal(),
 506             i_rst=ResetSignal(),
 507             o_memory_interface_fetch_address = mi.fetch_address,
 508             i_memory_interface_fetch_data = mi.fetch_data,
 509             i_memory_interface_fetch_valid = mi.fetch_valid,
 510             i_fetch_action = ft.action,
 511             i_target_pc = ft.target_pc,
 512             o_output_pc = ft.output_pc,
 513             o_output_instruction = ft.output_instruction,
 514             o_output_state = ft.output_state,
 515             i_reset_vector = reset_vector,
 516             i_mtvec = mtvec,
 517         )
 518         self.specials += fs
 519
 520         dc = Decoder()
 521
 522         cd = Instance("CPUDecoder", name="decoder",
 523             i_instruction = ft.output_instruction,
 524             o_funct7 = dc.funct7,
 525             o_funct3 = dc.funct3,
 526             o_rd = dc.rd,
 527             o_rs1 = dc.rs1,
 528             o_rs2 = dc.rs2,
 529             o_immediate = dc.immediate,
 530             o_opcode = dc.opcode,
 531             o_decode_action = dc.act
 532         )
 533         self.specials += cd
 534
 535         self.comb += self.regs.rs_a.eq(dc.rs1)
 536         self.comb += self.regs.rs_b.eq(dc.rs2)
 537
 538         load_store_address = Signal(32)
 539         load_store_address_low_2 = Signal(2)
 540         load_store_misaligned = Signal()
 541         unmasked_loaded_value = Signal(32)
 542         loaded_value = Signal(32)
 543
 544         lsc = Instance("CPULoadStoreCalc", name="cpu_loadstore_calc",
 545             i_dc_immediate = dc.immediate,
 546             i_dc_funct3 = dc.funct3,
 547             i_rs1 = self.regs.rs1,
 548             i_rs2 = self.regs.rs2,
 549             i_rw_data_in = mi.rw_data_in,
 550             i_rw_data_out = mi.rw_data_out,
 551             o_load_store_address = load_store_address,
 552             o_load_store_address_low_2 = load_store_address_low_2,
 553             o_load_store_misaligned = load_store_misaligned,
 554             o_loaded_value = loaded_value)
 555
 556         self.specials += lsc
 557
 558         # XXX rwaddr not 31:2 any more
 559         self.comb += mi.rw_address.eq(load_store_address[2:])
 560
 561         unshifted_load_store_byte_mask = Signal(4)
 562
 563         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc))
 564
 565         # XXX yuck.  this will cause migen simulation to fail
 566         # (however conversion to verilog works)
 567         self.comb += mi.rw_byte_mask.eq(
 568                 _Operator("<<", [unshifted_load_store_byte_mask,
 569                                         load_store_address_low_2]))
 570
 571         self.comb += mi.rw_active.eq(~self.reset
 572                         & (ft.output_state == FOS.valid)
 573                         & ~load_store_misaligned
 574                         & ((dc.act & (DA.load | DA.store)) != 0))
 575
 576         self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
 577
 578         # alu
 579         alu_a = Signal(32)
 580         alu_b = Signal(32)
 581         alu_result = Signal(32)
 582
 583         self.comb += alu_a.eq(self.regs.rs1)
 584         self.comb += alu_b.eq(Mux(dc.opcode[5],
 585                                   self.regs.rs2,
 586                                   dc.immediate))
 587
 588         ali = Instance("cpu_alu", name="alu",
 589             i_funct7 = dc.funct7,
 590             i_funct3 = dc.funct3,
 591             i_opcode = dc.opcode,
 592             i_a = alu_a,
 593             i_b = alu_b,
 594             o_result = alu_result
 595         )
 596         self.specials += ali
 597
 598         lui_auipc_result = Signal(32)
 599         self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
 600                                              dc.immediate,
 601                                              dc.immediate + ft.output_pc))
 602
 603         self.comb += ft.target_pc.eq(Cat(0,
 604                     Mux(dc.opcode != OP.jalr,
 605                                 ft.output_pc[1:32],
 606                                 self.regs.rs1[1:32] + dc.immediate[1:32])))
 607
 608         misaligned_jump_target = Signal()
 609         self.comb += misaligned_jump_target.eq(ft.target_pc[1])
 610
 611         branch_arg_a = Signal(32)
 612         branch_arg_b = Signal(32)
 613         self.comb += branch_arg_a.eq(Cat( self.regs.rs1[0:31],
 614                                           self.regs.rs1[31] ^ ~dc.funct3[1]))
 615         self.comb += branch_arg_b.eq(Cat( self.regs.rs2[0:31],
 616                                           self.regs.rs2[31] ^ ~dc.funct3[1]))
 617
 618         branch_taken = Signal()
 619         self.comb += branch_taken.eq(dc.funct3[0] ^
 620                                      Mux(dc.funct3[2],
 621                                          branch_arg_a < branch_arg_b,
 622                                          branch_arg_a == branch_arg_b))
 623
 624         m = M(self.comb, self.sync)
 625         mstatus = MStatus(self.comb, self.sync)
 626         mie = MIE(self.comb, self.sync)
 627         misa = Misa(self.comb, self.sync)
 628         mip = MIP()
 629
 630         mp = Instance("CPUMIP", name="cpu_mip",
 631             o_mip = mip.mip)
 632
 633         self.specials += mp
 634
 635         mii = Instance("CPUMIE", name="cpu_mie",
 636             o_mie = mie.mie,
 637             i_meie = mie.meie,
 638             i_mtie = mie.mtie,
 639             i_msie = mie.msie)
 640
 641         self.specials += mii
 642
 643         ms = Instance("CPUMStatus", name="cpu_mstatus",
 644             o_mstatus = mstatus.mstatus,
 645             i_mpie = mstatus.mpie,
 646             i_mie = mstatus.mie)
 647
 648         self.specials += ms
 649
 650         # CSR decoding
 651         csr = CSR(self.comb, self.sync, dc, self.regs.rs1)
 652
 653         fi = Instance("CPUFetchAction", name="cpu_fetch_action",
 654             o_fetch_action = ft.action,
 655             i_output_state = ft.output_state,
 656             i_dc_act = dc.act,
 657             i_load_store_misaligned = load_store_misaligned,
 658             i_mi_rw_wait = mi.rw_wait,
 659             i_mi_rw_address_valid = mi.rw_address_valid,
 660             i_branch_taken = branch_taken,
 661             i_misaligned_jump_target = misaligned_jump_target,
 662             i_csr_op_is_valid = csr.op_is_valid)
 663
 664         self.specials += fi
 665
 666         minfo = MInfo(self.comb)
 667
 668         self.sync += If(~self.reset,
 669                         self.main_block(mtvec, mip, minfo, misa, csr, mi, m,
 670                                         mstatus, mie, ft, dc,
 671                                         load_store_misaligned,
 672                                         loaded_value,
 673                                        alu_result,
 674                                        lui_auipc_result)
 675                      )
 676
 677 if __name__ == "__main__":
 678     example = CPU()
 679     print(verilog.convert(example,
 680          {
 681            example.tty_write,
 682            example.tty_write_data,
 683            example.tty_write_busy,
 684            example.switch_2,
 685            example.switch_3,
 686            example.led_1,
 687            example.led_3,
 688            }))