cpu.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 import string
  30 from migen import *
  31 from migen.fhdl import verilog
  32 from migen.fhdl.structure import _Operator
  33
  34 from riscvdefs import *
  35 from cpudefs import *
  36
  37 class MemoryInterface:
  38     fetch_address = Signal(32, name="memory_interface_fetch_address") # XXX [2:]
  39     fetch_data = Signal(32, name="memory_interface_fetch_data")
  40     fetch_valid = Signal(name="memory_interface_fetch_valid")
  41     rw_address= Signal(32, name="memory_interface_rw_address") # XXX [2:]
  42     rw_byte_mask = Signal(4, name="memory_interface_rw_byte_mask")
  43     rw_read_not_write = Signal(name="memory_interface_rw_read_not_write")
  44     rw_active = Signal(name="memory_interface_rw_active")
  45     rw_data_in = Signal(32, name="memory_interface_rw_data_in")
  46     rw_data_out = Signal(32, name="memory_interface_rw_data_out")
  47     rw_address_valid = Signal(name="memory_interface_rw_address_valid")
  48     rw_wait = Signal(name="memory_interface_rw_wait")
  49
  50
  51 class Decoder:
  52     funct7 = Signal(7, name="decoder_funct7")
  53     funct3 = Signal(3, name="decoder_funct3")
  54     rd = Signal(5, name="decoder_rd")
  55     rs1 = Signal(5, name="decoder_rs1")
  56     rs2 = Signal(5, name="decoder_rs2")
  57     immediate = Signal(32, name="decoder_immediate")
  58     opcode = Signal(7, name="decoder_opcode")
  59     act = Signal(decode_action, name="decoder_action")
  60
  61 class MStatus:
  62     def __init__(self, comb, sync):
  63         self.comb = comb
  64         self.sync = sync
  65         self.mpie = Signal(name="mstatus_mpie")
  66         self.mie = Signal(name="mstatus_mie")
  67         self.mprv = Signal(name="mstatus_mprv")
  68         self.tsr = Signal(name="mstatus_tsr")
  69         self.tw = Signal(name="mstatus_tw")
  70         self.tvm = Signal(name="mstatus_tvm")
  71         self.mxr = Signal(name="mstatus_mxr")
  72         self._sum = Signal(name="mstatus_sum")
  73         self.xs = Signal(name="mstatus_xs")
  74         self.fs = Signal(name="mstatus_fs")
  75         self.mpp = Signal(2, name="mstatus_mpp")
  76         self.spp = Signal(name="mstatus_spp")
  77         self.spie = Signal(name="mstatus_spie")
  78         self.upie = Signal(name="mstatus_upie")
  79         self.sie = Signal(name="mstatus_sie")
  80         self.uie = Signal(name="mstatus_uie")
  81
  82         for n in dir(self):
  83             if n in ['make', 'mpp', 'comb', 'sync'] or n.startswith("_"):
  84                 continue
  85             self.comb += getattr(self, n).eq(0x0)
  86         self.comb += self.mpp.eq(0b11)
  87
  88         self.sync += self.mie.eq(0)
  89         self.sync += self.mpie.eq(0)
  90
  91     def make(self):
  92         return Cat(
  93                 self.uie, self.sie, Constant(0), self.mie,
  94                 self.upie, self.spie, Constant(0), self.mpie,
  95                 self.spp, Constant(0, 2), self.mpp,
  96                 self.fs, self.xs, self.mprv, self._sum,
  97                 self.mxr, self.tvm, self.tw, self.tsr,
  98                 Constant(0, 8),
  99                 (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2))
 100                 )
 101
 102
 103 class MIE:
 104     def __init__(self, comb, sync):
 105         self.comb = comb
 106         self.sync = sync
 107         self.meie = Signal(name="mie_meie")
 108         self.mtie = Signal(name="mie_mtie")
 109         self.msie = Signal(name="mie_msie")
 110         self.seie = Signal(name="mie_seie")
 111         self.ueie = Signal(name="mie_ueie")
 112         self.stie = Signal(name="mie_stie")
 113         self.utie = Signal(name="mie_utie")
 114         self.ssie = Signal(name="mie_ssie")
 115         self.usie = Signal(name="mie_usie")
 116
 117         for n in dir(self):
 118             if n in ['make', 'comb', 'sync'] or n.startswith("_"):
 119                 continue
 120             self.comb += getattr(self, n).eq(0x0)
 121
 122         self.sync += self.meie.eq(0)
 123         self.sync += self.mtie.eq(0)
 124         self.sync += self.msie.eq(0)
 125
 126     def make(self):
 127         return Cat( self.usie, self.ssie, 0, self.msie,
 128                     self.utie, self.stie, 0, self.mtie,
 129                     self.ueie, self.seie, 0, self.meie, )
 130
 131
 132 class MIP:
 133     def __init__(self, comb, sync):
 134         self.comb = comb
 135         self.sync = sync
 136         self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts
 137         self.seip = Signal(name="mip_seip")
 138         self.ueip = Signal(name="mip_uiep")
 139         self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts
 140         self.stip = Signal(name="mip_stip")
 141         self.msip = Signal(name="mip_stip")
 142         self.utip = Signal(name="mip_utip")
 143         self.ssip = Signal(name="mip_ssip")
 144         self.usip = Signal(name="mip_usip")
 145
 146         for n in dir(self):
 147             if n in ['make', 'comb', 'sync'] or n.startswith("_"):
 148                 continue
 149             self.comb += getattr(self, n).eq(0x0)
 150
 151     def make(self):
 152         return Cat( self.usip, self.ssip, 0, self.msip,
 153                     self.utip, self.stip, 0, self.mtip,
 154                     self.ueip, self.seip, 0, self.meip, )
 155
 156
 157 class M:
 158     def __init__(self, comb, sync):
 159         self.comb = comb
 160         self.sync = sync
 161         self.mcause = Signal(32)
 162         self.mepc = Signal(32)
 163         self.mscratch = Signal(32)
 164         self.sync += self.mcause.eq(0)
 165         self.sync += self.mepc.eq(0) # 32'hXXXXXXXX;
 166         self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
 167
 168
 169 class Misa:
 170     def __init__(self, comb, sync):
 171         self.comb = comb
 172         self.sync = sync
 173         self.misa = Signal(32)
 174         cl = []
 175         for l in list(string.ascii_lowercase):
 176             value = 1 if l == 'i' else 0
 177             cl.append(Constant(value))
 178         cl.append(Constant(0, 4))
 179         cl.append(Constant(0b01, 2))
 180         self.comb += self.misa.eq(Cat(cl))
 181
 182
 183 class Fetch:
 184     def __init__(self, comb, sync):
 185         self.comb = comb
 186         self.sync = sync
 187         self.action = Signal(fetch_action, name="fetch_action")
 188         self.target_pc = Signal(32, name="fetch_target_pc")
 189         self.output_pc = Signal(32, name="fetch_output_pc")
 190         self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
 191         self.output_state = Signal(fetch_output_state,name="fetch_output_state")
 192
 193     def get_fetch_action(self, dc, load_store_misaligned, mi,
 194                          branch_taken, misaligned_jump_target,
 195                          csr_op_is_valid):
 196         c = {}
 197         c["default"] = self.action.eq(FA.default) # XXX should be 32'XXXXXXXX?
 198         c[FOS.empty] = self.action.eq(FA.default)
 199         c[FOS.trap] = self.action.eq(FA.ack_trap)
 200
 201         # illegal instruction -> error trap
 202         i= If((dc.act & DA.trap_illegal_instruction) != 0,
 203                  self.action.eq(FA.error_trap)
 204               )
 205
 206         # ecall / ebreak -> noerror trap
 207         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
 208                  self.action.eq(FA.noerror_trap))
 209
 210         # load/store: check alignment, check wait
 211         i = i.Elif((dc.act & (DA.load | DA.store)) != 0,
 212                 If((load_store_misaligned | ~mi.rw_address_valid),
 213                     self.action.eq(FA.error_trap) # misaligned or invalid addr
 214                 ).Elif(mi.rw_wait,
 215                     self.action.eq(FA.wait) # wait
 216                 ).Else(
 217                     self.action.eq(FA.default) # ok
 218                 )
 219               )
 220
 221         # fence
 222         i = i.Elif((dc.act & DA.fence) != 0,
 223                  self.action.eq(FA.fence))
 224
 225         # branch -> misaligned=error, otherwise jump
 226         i = i.Elif((dc.act & DA.branch) != 0,
 227                 If(misaligned_jump_target,
 228                     self.action.eq(FA.error_trap)
 229                 ).Else(
 230                     self.action.eq(FA.jump)
 231                 )
 232               )
 233
 234         # jal/jalr -> misaligned=error, otherwise jump
 235         i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
 236                 If(misaligned_jump_target,
 237                     self.action.eq(FA.error_trap)
 238                 ).Else(
 239                     self.action.eq(FA.jump)
 240                 )
 241               )
 242
 243         # csr -> opvalid=ok, else error trap
 244         i = i.Elif((dc.act & DA.csr) != 0,
 245                 If(csr_op_is_valid,
 246                     self.action.eq(FA.default)
 247                 ).Else(
 248                     self.action.eq(FA.error_trap)
 249                 )
 250               )
 251
 252         c[FOS.valid] = i
 253
 254         return Case(self.output_state, c)
 255
 256 class CSR:
 257     def __init__(self, comb, sync, dc, register_rs1):
 258         self.comb = comb
 259         self.sync = sync
 260         self.number = Signal(12, name="csr_number")
 261         self.input_value = Signal(32, name="csr_input_value")
 262         self.reads = Signal(name="csr_reads")
 263         self.writes = Signal(name="csr_writes")
 264         self.op_is_valid = Signal(name="csr_op_is_valid")
 265
 266         self.comb += self.number.eq(dc.immediate)
 267         self.comb += self.input_value.eq(Mux(dc.funct3[2],
 268                                             dc.rs1,
 269                                             register_rs1))
 270         self.comb += self.reads.eq(dc.funct3[1] | (dc.rd != 0))
 271         self.comb += self.writes.eq(~dc.funct3[1] | (dc.rs1 != 0))
 272
 273         self.comb += self.get_csr_op_is_valid()
 274
 275     def get_csr_op_is_valid(self):
 276         """ determines if a CSR is valid
 277         """
 278         c = {}
 279         # invalid csrs
 280         for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr,
 281                   csr_uie, csr_utvec, csr_uscratch, csr_uepc,
 282                   csr_ucause, csr_utval, csr_uip, csr_sstatus,
 283                   csr_sedeleg, csr_sideleg, csr_sie, csr_stvec,
 284                   csr_scounteren, csr_sscratch, csr_sepc, csr_scause,
 285                   csr_stval, csr_sip, csr_satp, csr_medeleg,
 286                   csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]:
 287             c[f] = self.op_is_valid.eq(0)
 288
 289         # not-writeable -> ok
 290         for f in [csr_cycle, csr_time, csr_instret, csr_cycleh,
 291                   csr_timeh, csr_instreth, csr_mvendorid, csr_marchid,
 292                   csr_mimpid, csr_mhartid]:
 293             c[f] = self.op_is_valid.eq(~self.writes)
 294
 295         # valid csrs
 296         for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec,
 297                   csr_mscratch, csr_mepc, csr_mcause, csr_mip]:
 298             c[f] = self.op_is_valid.eq(1)
 299
 300         # not implemented / default
 301         for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret,
 302                   csr_mcycleh, csr_minstreth, "default"]:
 303             c[f] = self.op_is_valid.eq(0)
 304
 305         return Case(self.number, c)
 306
 307     def evaluate_csr_funct3_op(self, funct3, previous, written):
 308         c = { "default": written.eq(Constant(0, 32))}
 309         for f in [F3.csrrw, F3.csrrwi]:
 310             c[f] = written.eq(self.input_value)
 311         for f in [F3.csrrs, F3.csrrsi]:
 312             c[f] = written.eq(self.input_value | previous)
 313         for f in [F3.csrrc, F3.csrrci]:
 314             c[f] = written.eq(~self.input_value & previous)
 315         return Case(funct3, c)
 316
 317
 318 class MInfo:
 319     def __init__(self, comb):
 320         self.comb = comb
 321         # TODO
 322         self.cycle_counter   = Signal(64); # TODO: implement cycle_counter
 323         self.time_counter    = Signal(64); # TODO: implement time_counter
 324         self.instret_counter = Signal(64); # TODO: implement instret_counter
 325
 326         self.mvendorid = Signal(32)
 327         self.marchid = Signal(32)
 328         self.mimpid = Signal(32)
 329         self.mhartid = Signal(32)
 330         self.comb += self.mvendorid.eq(Constant(0, 32))
 331         self.comb += self.marchid.eq(Constant(0, 32))
 332         self.comb += self.mimpid.eq(Constant(0, 32))
 333         self.comb += self.mhartid.eq(Constant(0, 32))
 334
 335
 336 class CPU(Module):
 337     """
 338     """
 339
 340     def get_ls_misaligned(self, ls, funct3, load_store_address_low_2):
 341         """ returns whether a load/store is misaligned
 342         """
 343         return Case(funct3[:2],
 344                 { F3.sb: ls.eq(Constant(0)),
 345                   F3.sh: ls.eq(load_store_address_low_2[0] != 0),
 346                   F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)),
 347                   "default": ls.eq(Constant(1))
 348                 })
 349
 350     def get_lsbm(self, dc):
 351         return Cat(Constant(1),
 352                    Mux((dc.funct3[1] | dc.funct3[0]),
 353                        Constant(1), Constant(0)),
 354                    Mux((dc.funct3[1]),
 355                        Constant(0b11, 2), Constant(0, 2)))
 356
 357     # XXX this happens to get done by various self.sync actions
 358     #def reset_to_initial(self, m, mstatus, mie, registers):
 359     #    return [m.mcause.eq(0),
 360     #            ]
 361
 362     def write_register(self, register_number, value):
 363         return If(register_number != 0,
 364                   self.registers[register_number].eq(value)
 365                )
 366
 367     def handle_trap(self, m, ms, ft, dc, load_store_misaligned):
 368         s = [ms.mpie.eq(ms.mie),
 369              ms.mie.eq(0),
 370              m.mepc.eq(Mux(ft.action == FA.noerror_trap,
 371                            ft.output_pc + 4,
 372                            ft.output_pc))]
 373
 374         # fetch action ack trap
 375         i = If(ft.action == FA.ack_trap,
 376                 m.mcause.eq(cause_instruction_access_fault)
 377               )
 378
 379         # ecall/ebreak
 380         i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
 381                 m.mcause.eq(Mux(dc.immediate[0],
 382                                 cause_machine_environment_call,
 383                                 cause_breakpoint))
 384               )
 385
 386         # load
 387         i = i.Elif((dc.act & DA.load) != 0,
 388                 If(load_store_misaligned,
 389                     m.mcause.eq(cause_load_address_misaligned)
 390                 ).Else(
 391                     m.mcause.eq(cause_load_access_fault)
 392                 )
 393               )
 394
 395         # store
 396         i = i.Elif((dc.act & DA.store) != 0,
 397                 If(load_store_misaligned,
 398                     m.mcause.eq(cause_store_amo_address_misaligned)
 399                 ).Else(
 400                     m.mcause.eq(cause_store_amo_access_fault)
 401                 )
 402               )
 403
 404         # jal/jalr -> misaligned=error, otherwise jump
 405         i = i.Elif((dc.act & (DA.jal | DA.jalr | DA.branch)) != 0,
 406                 m.mcause.eq(cause_instruction_address_misaligned)
 407               )
 408
 409         # defaults to illegal instruction
 410         i = i.Else(m.mcause.eq(cause_illegal_instruction))
 411
 412         s.append(i)
 413         return s
 414
 415     def main_block(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
 416                          ft, dc,
 417                          load_store_misaligned,
 418                          loaded_value, alu_result,
 419                          lui_auipc_result):
 420         c = {}
 421         c[FOS.empty] = []
 422         c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc,
 423                                        load_store_misaligned)
 424         c[FOS.valid] = self.handle_valid(mtvec, mip, minfo, misa, csr, mi, m,
 425                                        mstatus, mie, ft, dc,
 426                                        load_store_misaligned,
 427                                        loaded_value,
 428                                        alu_result,
 429                                        lui_auipc_result)
 430         return Case(ft.output_state, c)
 431
 432     def handle_valid(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
 433                            ft, dc,
 434                            load_store_misaligned,
 435                            loaded_value, alu_result,
 436                            lui_auipc_result):
 437         # fetch action ack trap
 438         i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
 439                 self.handle_trap(m, mstatus, ft, dc,
 440                                        load_store_misaligned)
 441               )
 442
 443         # load
 444         i = i.Elif((dc.act & DA.load) != 0,
 445                 If(~mi.rw_wait,
 446                     self.write_register(dc.rd, loaded_value)
 447                 )
 448               )
 449
 450         # op or op_immediate
 451         i = i.Elif((dc.act & DA.op_op_imm) != 0,
 452                 self.write_register(dc.rd, alu_result)
 453               )
 454
 455         # lui or auipc
 456         i = i.Elif((dc.act & DA.lui_auipc) != 0,
 457                 self.write_register(dc.rd, lui_auipc_result)
 458               )
 459
 460         # jal/jalr
 461         i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
 462                 self.write_register(dc.rd, ft.output_pc + 4)
 463               )
 464
 465         i = i.Elif((dc.act & DA.csr) != 0,
 466                 self.handle_csr(mtvec, mip, minfo, misa, mstatus, mie, m,
 467                                 dc, csr)
 468               )
 469
 470         # fence, store, branch
 471         i = i.Elif((dc.act & (DA.fence | DA.fence_i |
 472                               DA.store | DA.branch)) != 0,
 473                 # do nothing
 474               )
 475
 476         return i
 477
 478     def handle_csr(self, mtvec, mip, minfo, misa, mstatus, mie, m, dc, csr):
 479         csr_output_value = Signal(32)
 480         csr_written_value = Signal(32)
 481         c = {}
 482
 483         # cycle
 484         c[csr_cycle]  = csr_output_value.eq(minfo.cycle_counter[0:32])
 485         c[csr_cycleh] = csr_output_value.eq(minfo.cycle_counter[32:64])
 486         # time
 487         c[csr_time]  = csr_output_value.eq(minfo.time_counter[0:32])
 488         c[csr_timeh] = csr_output_value.eq(minfo.time_counter[32:64])
 489         # instret
 490         c[csr_instret]  = csr_output_value.eq(minfo.instret_counter[0:32])
 491         c[csr_instreth] = csr_output_value.eq(minfo.instret_counter[32:64])
 492         # mvendorid/march/mimpl/mhart
 493         c[csr_mvendorid] = csr_output_value.eq(minfo.mvendorid)
 494         c[csr_marchid  ] = csr_output_value.eq(minfo.marchid  )
 495         c[csr_mimpid   ] = csr_output_value.eq(minfo.mimpid   )
 496         c[csr_mhartid  ] = csr_output_value.eq(minfo.mhartid  )
 497         # misa
 498         c[csr_misa     ] = csr_output_value.eq(misa.misa)
 499         # mstatus
 500         c[csr_mstatus  ] = [
 501             csr_output_value.eq(mstatus.make()),
 502             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 503                                                   csr_written_value),
 504             mstatus.mpie.eq(csr_written_value[7]),
 505             mstatus.mie.eq(csr_written_value[3])
 506         ]
 507         # mie
 508         c[csr_mie      ] = [
 509             csr_output_value.eq(mie.make()),
 510             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 511                                                   csr_written_value),
 512             mie.meie.eq(csr_written_value[11]),
 513             mie.mtie.eq(csr_written_value[7]),
 514             mie.msie.eq(csr_written_value[3]),
 515         ]
 516         # mtvec
 517         c[csr_mtvec    ] = csr_output_value.eq(mtvec)
 518         # mscratch
 519         c[csr_mscratch ] = [
 520             csr_output_value.eq(m.mscratch),
 521             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 522                                                   csr_written_value),
 523             If(csr.writes,
 524                 m.mscratch.eq(csr_written_value),
 525             )
 526         ]
 527         # mepc
 528         c[csr_mepc ] = [
 529             csr_output_value.eq(m.mepc),
 530             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 531                                                   csr_written_value),
 532             If(csr.writes,
 533                 m.mepc.eq(csr_written_value),
 534             )
 535         ]
 536
 537         # mcause
 538         c[csr_mcause ] = [
 539             csr_output_value.eq(m.mcause),
 540             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 541                                                   csr_written_value),
 542             If(csr.writes,
 543                 m.mcause.eq(csr_written_value),
 544             )
 545         ]
 546
 547         # mip
 548         c[csr_mip  ] = [
 549             csr_output_value.eq(mip.make()),
 550             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
 551                                                   csr_written_value),
 552         ]
 553
 554         return [Case(csr.number, c),
 555                 If(csr.reads,
 556                     self.write_register(dc.rd, csr_output_value)
 557                 )]
 558
 559         """
 560                 `csr_mip: begin
 561                     csr_output_value = 0;
 562                     csr_output_value[11] = mip_meip;
 563                     csr_output_value[9] = mip_seip;
 564                     csr_output_value[8] = mip_ueip;
 565                     csr_output_value[7] = mip_mtip;
 566                     csr_output_value[5] = mip_stip;
 567                     csr_output_value[4] = mip_utip;
 568                     csr_output_value[3] = mip_msip;
 569                     csr_output_value[1] = mip_ssip;
 570                     csr_output_value[0] = mip_usip;
 571                 end
 572                 endcase
 573         end
 574         endcase
 575     end
 576         """
 577     def __init__(self):
 578         self.clk = ClockSignal()
 579         self.reset = ResetSignal()
 580         self.tty_write = Signal()
 581         self.tty_write_data = Signal(8)
 582         self.tty_write_busy = Signal()
 583         self.switch_2 = Signal()
 584         self.switch_3 = Signal()
 585         self.led_1 = Signal()
 586         self.led_3 = Signal()
 587
 588         ram_size = Constant(0x8000)
 589         ram_start = Constant(0x10000, 32)
 590         reset_vector = Signal(32)
 591         mtvec = Signal(32)
 592
 593         reset_vector.eq(ram_start)
 594         mtvec.eq(ram_start + 0x40)
 595
 596         l = []
 597         for i in range(31):
 598             r = Signal(32, name="register%d" % i)
 599             l.append(r)
 600             self.sync += r.eq(Constant(0, 32))
 601         self.registers = Array(l)
 602
 603         mi = MemoryInterface()
 604
 605         mii = Instance("cpu_memory_interface", name="memory_instance",
 606                     p_ram_size = ram_size,
 607                     p_ram_start = ram_start,
 608                     i_clk=ClockSignal(),
 609                     i_rst=ResetSignal(),
 610                     i_fetch_address = mi.fetch_address,
 611                     o_fetch_data = mi.fetch_data,
 612                     o_fetch_valid = mi.fetch_valid,
 613                     i_rw_address = mi.rw_address,
 614                     i_rw_byte_mask = mi.rw_byte_mask,
 615                     i_rw_read_not_write = mi.rw_read_not_write,
 616                     i_rw_active = mi.rw_active,
 617                     i_rw_data_in = mi.rw_data_in,
 618                     o_rw_data_out = mi.rw_data_out,
 619                     o_rw_address_valid = mi.rw_address_valid,
 620                     o_rw_wait = mi.rw_wait,
 621                     o_tty_write = self.tty_write,
 622                     o_tty_write_data = self.tty_write_data,
 623                     i_tty_write_busy = self.tty_write_busy,
 624                     i_switch_2 = self.switch_2,
 625                     i_switch_3 = self.switch_3,
 626                     o_led_1 = self.led_1,
 627                     o_led_3 = self.led_3
 628                   )
 629         self.specials += mii
 630
 631         ft = Fetch(self.comb, self.sync)
 632
 633         fs = Instance("CPUFetchStage", name="fetch_stage",
 634             i_clk=ClockSignal(),
 635             i_rst=ResetSignal(),
 636             o_memory_interface_fetch_address = mi.fetch_address,
 637             i_memory_interface_fetch_data = mi.fetch_data,
 638             i_memory_interface_fetch_valid = mi.fetch_valid,
 639             i_fetch_action = ft.action,
 640             i_target_pc = ft.target_pc,
 641             o_output_pc = ft.output_pc,
 642             o_output_instruction = ft.output_instruction,
 643             o_output_state = ft.output_state,
 644             i_reset_vector = reset_vector,
 645             i_mtvec = mtvec,
 646         )
 647         self.specials += fs
 648
 649         dc = Decoder()
 650
 651         cd = Instance("CPUDecoder", name="decoder",
 652             i_instruction = ft.output_instruction,
 653             o_funct7 = dc.funct7,
 654             o_funct3 = dc.funct3,
 655             o_rd = dc.rd,
 656             o_rs1 = dc.rs1,
 657             o_rs2 = dc.rs2,
 658             o_immediate = dc.immediate,
 659             o_opcode = dc.opcode,
 660             o_decode_action = dc.act
 661         )
 662         self.specials += cd
 663
 664         register_rs1 = Signal(32)
 665         register_rs2 = Signal(32)
 666         self.comb += If(dc.rs1 == 0,
 667                         register_rs1.eq(0)
 668                      ).Else(
 669                         register_rs1.eq(self.registers[dc.rs1-1]))
 670         self.comb += If(dc.rs2 == 0,
 671                         register_rs2.eq(0)
 672                      ).Else(
 673                         register_rs2.eq(self.registers[dc.rs2-1]))
 674
 675         load_store_address = Signal(32)
 676         load_store_address_low_2 = Signal(2)
 677
 678         self.comb += load_store_address.eq(dc.immediate + register_rs1)
 679         self.comb += load_store_address_low_2.eq(
 680                             dc.immediate[:2] + register_rs1[:2])
 681
 682         load_store_misaligned = Signal()
 683
 684         lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3,
 685                                      load_store_address_low_2)
 686         self.comb += lsa
 687
 688         # XXX rwaddr not 31:2 any more
 689         self.comb += mi.rw_address.eq(load_store_address[2:])
 690
 691         unshifted_load_store_byte_mask = Signal(4)
 692
 693         self.comb += unshifted_load_store_byte_mask.eq(self.get_lsbm(dc))
 694
 695         # XXX yuck.  this will cause migen simulation to fail
 696         # (however conversion to verilog works)
 697         self.comb += mi.rw_byte_mask.eq(
 698                 _Operator("<<", [unshifted_load_store_byte_mask,
 699                                         load_store_address_low_2]))
 700
 701         # XXX not obvious
 702         b3 = Mux(load_store_address_low_2[1],
 703                  Mux(load_store_address_low_2[0], register_rs2[0:8],
 704                                                   register_rs2[8:16]),
 705                  Mux(load_store_address_low_2[0], register_rs2[16:24],
 706                                                   register_rs2[24:32]))
 707         b2 = Mux(load_store_address_low_2[1], register_rs2[0:8],
 708                                               register_rs2[16:24])
 709         b1 = Mux(load_store_address_low_2[0], register_rs2[0:8],
 710                                               register_rs2[8:16])
 711         b0 = register_rs2[0:8]
 712
 713         self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3))
 714
 715         # XXX not obvious
 716         unmasked_loaded_value = Signal(32)
 717
 718         b0 = Mux(load_store_address_low_2[1],
 719                  Mux(load_store_address_low_2[0], mi.rw_data_out[24:32],
 720                                                   mi.rw_data_out[16:24]),
 721                  Mux(load_store_address_low_2[0], mi.rw_data_out[15:8],
 722                                                   mi.rw_data_out[0:8]))
 723         b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31],
 724                                               mi.rw_data_out[8:16])
 725         b23 = mi.rw_data_out[16:32]
 726
 727         self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
 728
 729         # XXX not obvious
 730         loaded_value = Signal(32)
 731
 732         b0 = unmasked_loaded_value[0:8]
 733         b1 = Mux(dc.funct3[0:2] == 0,
 734                 Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8),
 735                 unmasked_loaded_value[8:16])
 736         b2 = Mux(dc.funct3[1] == 0,
 737                 Replicate(~dc.funct3[2] &
 738                            Mux(dc.funct3[0], unmasked_loaded_value[15],
 739                                                   unmasked_loaded_value[7]),
 740                           16),
 741                 unmasked_loaded_value[16:32])
 742
 743         self.comb += loaded_value.eq(Cat(b0, b1, b2))
 744
 745         self.comb += mi.rw_active.eq(~self.reset
 746                         & (ft.output_state == FOS.valid)
 747                         & ~load_store_misaligned
 748                         & ((dc.act & (DA.load | DA.store)) != 0))
 749
 750         self.comb += mi.rw_read_not_write.eq(~dc.opcode[5])
 751
 752         # alu
 753         alu_a = Signal(32)
 754         alu_b = Signal(32)
 755         alu_result = Signal(32)
 756
 757         self.comb += alu_a.eq(register_rs1)
 758         self.comb += alu_b.eq(Mux(dc.opcode[5],
 759                                   register_rs2,
 760                                   dc.immediate))
 761
 762         ali = Instance("cpu_alu", name="alu",
 763             i_funct7 = dc.funct7,
 764             i_funct3 = dc.funct3,
 765             i_opcode = dc.opcode,
 766             i_a = alu_a,
 767             i_b = alu_b,
 768             o_result = alu_result
 769         )
 770         self.specials += ali
 771
 772         lui_auipc_result = Signal(32)
 773         self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
 774                                              dc.immediate,
 775                                              dc.immediate + ft.output_pc))
 776
 777         self.comb += ft.target_pc.eq(Cat(0,
 778                     Mux(dc.opcode != OP.jalr,
 779                                 ft.output_pc[1:32],
 780                                 register_rs1[1:32] + dc.immediate[1:32])))
 781
 782         misaligned_jump_target = Signal()
 783         self.comb += misaligned_jump_target.eq(ft.target_pc[1])
 784
 785         branch_arg_a = Signal(32)
 786         branch_arg_b = Signal(32)
 787         self.comb += branch_arg_a.eq(Cat( register_rs1[0:31],
 788                                           register_rs1[31] ^ ~dc.funct3[1]))
 789         self.comb += branch_arg_b.eq(Cat( register_rs2[0:31],
 790                                           register_rs2[31] ^ ~dc.funct3[1]))
 791
 792         branch_taken = Signal()
 793         self.comb += branch_taken.eq(dc.funct3[0] ^
 794                                      Mux(dc.funct3[2],
 795                                          branch_arg_a < branch_arg_b,
 796                                          branch_arg_a == branch_arg_b))
 797
 798         m = M(self.comb, self.sync)
 799         mstatus = MStatus(self.comb, self.sync)
 800         mie = MIE(self.comb, self.sync)
 801         misa = Misa(self.comb, self.sync)
 802         mip = MIP(self.comb, self.sync)
 803
 804         # CSR decoding
 805         csr = CSR(self.comb, self.sync, dc, register_rs1)
 806
 807         self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi,
 808                                  branch_taken, misaligned_jump_target,
 809                                  csr.op_is_valid)
 810
 811         minfo = MInfo(self.comb)
 812
 813         self.sync += If(~self.reset,
 814                         self.main_block(mtvec, mip, minfo, misa, csr, mi, m,
 815                                         mstatus, mie, ft, dc,
 816                                         load_store_misaligned,
 817                                         loaded_value,
 818                                        alu_result,
 819                                        lui_auipc_result)
 820                      )
 821
 822 if __name__ == "__main__":
 823     example = CPU()
 824     print(verilog.convert(example,
 825          {
 826            example.tty_write,
 827            example.tty_write_data,
 828            example.tty_write_busy,
 829            example.switch_2,
 830            example.switch_3,
 831            example.led_1,
 832            example.led_3,
 833            }))
 834
 835 """
 836
 837     always @(posedge clk) begin:main_block
 838         if(reset) begin
 839             reset_to_initial();
 840             disable main_block;
 841         end
 842         case(fetch_output_state)
 843         `fetch_output_state_empty: begin
 844         end
 845         `fetch_output_state_trap: begin
 846             handle_trap();
 847         end
 848         `fetch_output_state_valid: begin:valid
 849             if((fetch_action == `fetch_action_error_trap) | (fetch_action == `fetch_action_noerror_trap)) begin
 850                 handle_trap();
 851             end
 852             else if((decode_action & `decode_action_load) != 0) begin
 853                 if(~memory_interface_rw_wait)
 854                     write_register(decoder_rd, loaded_value);
 855             end
 856             else if((decode_action & `decode_action_op_op_imm) != 0) begin
 857                 write_register(decoder_rd, alu_result);
 858             end
 859             else if((decode_action & `decode_action_lui_auipc) != 0) begin
 860                 write_register(decoder_rd, lui_auipc_result);
 861             end
 862             else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
 863                 write_register(decoder_rd, fetch_output_pc + 4);
 864             end
 865             else if((decode_action & `decode_action_csr) != 0) begin:csr
 866                 reg [31:0] csr_output_value;
 867                 reg [31:0] csr_written_value;
 868                 csr_output_value = 32'hXXXXXXXX;
 869                 csr_written_value = 32'hXXXXXXXX;
 870                 case(csr_number)
 871                 `csr_cycle: begin
 872                     csr_output_value = cycle_counter[31:0];
 873                 end
 874                 `csr_time: begin
 875                     csr_output_value = time_counter[31:0];
 876                 end
 877                 `csr_instret: begin
 878                     csr_output_value = instret_counter[31:0];
 879                 end
 880                 `csr_cycleh: begin
 881                     csr_output_value = cycle_counter[63:32];
 882                 end
 883                 `csr_timeh: begin
 884                     csr_output_value = time_counter[63:32];
 885                 end
 886                 `csr_instreth: begin
 887                     csr_output_value = instret_counter[63:32];
 888                 end
 889                 `csr_mvendorid: begin
 890                     csr_output_value = mvendorid;
 891                 end
 892                 `csr_marchid: begin
 893                     csr_output_value = marchid;
 894                 end
 895                 `csr_mimpid: begin
 896                     csr_output_value = mimpid;
 897                 end
 898                 `csr_mhartid: begin
 899                     csr_output_value = mhartid;
 900                 end
 901                 `csr_misa: begin
 902                     csr_output_value = misa;
 903                 end
 904                 `csr_mstatus: begin
 905                     csr_output_value = make_mstatus(mstatus_tsr,
 906                                                     mstatus_tw,
 907                                                     mstatus_tvm,
 908                                                     mstatus_mxr,
 909                                                     mstatus_sum,
 910                                                     mstatus_mprv,
 911                                                     mstatus_xs,
 912                                                     mstatus_fs,
 913                                                     mstatus_mpp,
 914                                                     mstatus_spp,
 915                                                     mstatus_mpie,
 916                                                     mstatus_spie,
 917                                                     mstatus_upie,
 918                                                     mstatus_mie,
 919                                                     mstatus_sie,
 920                                                     mstatus_uie);
 921                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 922                     if(csr_writes) begin
 923                         mstatus_mpie = csr_written_value[7];
 924                         mstatus_mie = csr_written_value[3];
 925                     end
 926                 end
 927                 `csr_mie: begin
 928                     csr_output_value = 0;
 929                     csr_output_value[11] = mie_meie;
 930                     csr_output_value[9] = mie_seie;
 931                     csr_output_value[8] = mie_ueie;
 932                     csr_output_value[7] = mie_mtie;
 933                     csr_output_value[5] = mie_stie;
 934                     csr_output_value[4] = mie_utie;
 935                     csr_output_value[3] = mie_msie;
 936                     csr_output_value[1] = mie_ssie;
 937                     csr_output_value[0] = mie_usie;
 938                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 939                     if(csr_writes) begin
 940                         mie_meie = csr_written_value[11];
 941                         mie_mtie = csr_written_value[7];
 942                         mie_msie = csr_written_value[3];
 943                     end
 944                 end
 945                 `csr_mtvec: begin
 946                     csr_output_value = mtvec;
 947                 end
 948                 `csr_mscratch: begin
 949                     csr_output_value = mscratch;
 950                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 951                     if(csr_writes)
 952                         mscratch = csr_written_value;
 953                 end
 954                 `csr_mepc: begin
 955                     csr_output_value = mepc;
 956                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 957                     if(csr_writes)
 958                         mepc = csr_written_value;
 959                 end
 960                 `csr_mcause: begin
 961                     csr_output_value = mcause;
 962                     csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value);
 963                     if(csr_writes)
 964                         mcause = csr_written_value;
 965                 end
 966                 `csr_mip: begin
 967                     csr_output_value = 0;
 968                     csr_output_value[11] = mip_meip;
 969                     csr_output_value[9] = mip_seip;
 970                     csr_output_value[8] = mip_ueip;
 971                     csr_output_value[7] = mip_mtip;
 972                     csr_output_value[5] = mip_stip;
 973                     csr_output_value[4] = mip_utip;
 974                     csr_output_value[3] = mip_msip;
 975                     csr_output_value[1] = mip_ssip;
 976                     csr_output_value[0] = mip_usip;
 977                 end
 978                 endcase
 979                 if(csr_reads)
 980                     write_register(decoder_rd, csr_output_value);
 981             end
 982             else if((decode_action & (`decode_action_fence | `decode_action_fence_i | `decode_action_store | `decode_action_branch)) != 0) begin
 983                 // do nothing
 984             end
 985         end
 986         endcase
 987     end
 988
 989 endmodule
 990 """
 991