cpu_fetch_stage.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 """
  25
  26 from migen import *
  27 from migen.fhdl import verilog
  28
  29 from riscvdefs import *
  30 from cpudefs import *
  31
  32 reset_vector = 32'hXXXXXXXX;
  33 mtvec = 32'hXXXXXXXX;
  34
  35 class CPUFetchStage(Module):
  36     def __init__(self):
  37         self.clk = ClockSignal()
  38         self.reset = ResetSignal()
  39         #output [31:2] memory_interface_fetch_address,
  40         self.memory_interface_fetch_address = Signal(32)[2:]
  41         #input [31:0] memory_interface_fetch_data,
  42         self.memory_interface_fetch_data = Signal(32)
  43         self.memory_interface_fetch_valid = Signal()
  44         self.fetch_action = Signal(fetch_action)
  45         self.target_pc = Signal(32)
  46         self.output_pc = Signal(32, reset=reset_vector)
  47         self.output_instruction = Signal(32)
  48         self.output_state = Signal(fetch_output_state,
  49                                    reset=fetch_output_state_empty)
  50
  51         self.comb += [
  52             self.cd_sys.clk.eq(self.clk),
  53             self.cd_sys.rst.eq(self.reset)
  54         ]
  55
  56         fetch_pc = Signal(32, reset=reset_vector)
  57
  58         self.sync += If(fetch_action != fetch_action_wait,
  59                         output_pc.eq(fetch_pc)).
  60                      Else( output_pc.eq(output_pc)) # hmmm...
  61         #self.sync += output_pc.eq((fetch_action == `fetch_action_wait) ?
  62         #                          output_pc : fetch_pc);
  63
  64         memory_interface_fetch_address = fetch_pc[2:]
  65
  66         initial output_pc <= reset_vector;
  67         initial output_state <= `fetch_output_state_empty;
  68
  69         delayed_instruction = Signal(32, reset=0);
  70         delayed_instruction_valid = Signal(reset=0);
  71
  72         self.sync += delayed_instruction.eq(output_instruction)
  73         self.sync += output_state.eq(fetch_output_state_empty)
  74
  75         self.comb += If(delayed_instruction_valid,
  76                     output_instruction.eq(delayed_instruction)
  77                 ).Else(
  78                     output_instruction.eq(memory_interface_fetch_data)
  79                 )
  80
  81         self.sync += delayed_instruction_valid.eq(fetch_action ==
  82                                                   fetch_action_wait)
  83
  84         fc = {
  85             fetch_action_ack_trap:
  86                 If(memory_interface_fetch_valid,
  87                    [fetch_pc.eq(fetch_pc + 4),
  88                     output_state.eq(fetch_output_state_valid)]
  89                 ).Else(
  90                    [fetch_pc.eq(mtvec),
  91                     output_state.eq(fetch_output_state_trap)]
  92                 ),
  93             fetch_action_fence:
  94                 [ fetch_pc.eq(output_pc + 4),
  95                   output_state.eq(fetch_output_state_empty)
  96                 ],
  97             fetch_action_jump:
  98                 [ fetch_pc.eq(target_pc),
  99                   output_state.eq(fetch_output_state_empty)
 100                 ],
 101             fetch_action_error_trap,
 102                    [fetch_pc.eq(mtvec),
 103                     output_state.eq(fetch_output_state_empty)
 104                 ],
 105             fetch_action_wait:
 106                    [fetch_pc.eq(fetch_pc),
 107                     output_state.eq(fetch_output_state_valid)
 108                 ]
 109         }
 110         fc[fetch_action_default] = fc[fetch_action_ack_trap]
 111         fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
 112         self.sync += Case(fetch_action, fc).makedefault(fetch_action_default)
 113