cpu_fetch_stage.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 """
  25
  26 from migen import *
  27 from migen.fhdl import verilog
  28
  29 from riscvdefs import *
  30 from cpudefs import *
  31
  32 reset_vector = 32'hXXXXXXXX;
  33 mtvec = 32'hXXXXXXXX;
  34
  35 class CPUFetchStage(Module):
  36     def __init__(self):
  37         self.clk = ClockSignal()
  38         self.reset = ResetSignal()
  39         #output [31:2] memory_interface_fetch_address,
  40         self.memory_interface_fetch_address = Signal(32)[2:]
  41         #input [31:0] memory_interface_fetch_data,
  42         self.memory_interface_fetch_data = Signal(32)
  43         self.memory_interface_fetch_valid = Signal()
  44         input `fetch_action fetch_action,
  45         input [31:0] target_pc,
  46         self.output_pc = Signal(32, reset=reset_vector)
  47         self.output_instruction = Signal(32)
  48         output reg `fetch_output_state output_state
  49
  50         self.comb += [
  51             self.cd_sys.clk.eq(self.clk),
  52             self.cd_sys.rst.eq(self.reset)
  53         ]
  54
  55         fetch_pc = Signal(32, reset=reset_vector)
  56
  57         self.sync += output_pc.eq((fetch_action == `fetch_action_wait) ? output_pc : fetch_pc);
  58
  59         memory_interface_fetch_address = fetch_pc[31:2];
  60
  61         initial output_pc <= reset_vector;
  62         initial output_state <= `fetch_output_state_empty;
  63
  64         delayed_instruction = Signal(32, reset=0);
  65         delayed_instruction_valid = Signal(reset=0);
  66
  67         self.sync += delayed_instruction.eq(output_instruction)
  68
  69         assign output_instruction = delayed_instruction_valid ? delayed_instruction : memory_interface_fetch_data;
  70
  71         self.sync += delayed_instruction_valid.eq(fetch_action == `fetch_action_wait)
  72
  73         always @(posedge clk or posedge reset) begin
  74             if(reset) begin
  75                 output_state <= `fetch_output_state_empty;
  76             end
  77             else begin
  78                 case(fetch_action)
  79                 `fetch_action_default,
  80                 `fetch_action_ack_trap: begin
  81                     if(memory_interface_fetch_valid) begin
  82                         fetch_pc <= fetch_pc + 4;
  83                         output_state <= `fetch_output_state_valid;
  84                     end
  85                     else begin
  86                         fetch_pc <= mtvec;
  87                         output_state <= `fetch_output_state_trap;
  88                     end
  89                 end
  90                 `fetch_action_fence: begin
  91                     fetch_pc <= output_pc + 4;
  92                     output_state <= `fetch_output_state_empty;
  93                 end
  94                 `fetch_action_jump: begin
  95                     fetch_pc <= target_pc;
  96                     output_state <= `fetch_output_state_empty;
  97                 end
  98                 `fetch_action_error_trap,
  99                 `fetch_action_noerror_trap: begin
 100                     fetch_pc <= mtvec;
 101                     output_state <= `fetch_output_state_empty;
 102                 end
 103                 `fetch_action_wait: begin
 104                     fetch_pc <= fetch_pc;
 105                     output_state <= `fetch_output_state_valid;
 106                 end
 107                 endcase
 108             end
 109         end
 110     endmodule