cpu_handle_trap.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 import string
  30 from migen import *
  31 from migen.fhdl import verilog
  32 from migen.fhdl.structure import _Operator
  33
  34 from riscvdefs import *
  35 from cpudefs import *
  36
  37
  38 class CPUHandleTrap(Module):
  39     """
  40     """
  41
  42     def __init__(self):
  43         Module.__init__(self)
  44         self.clk = ClockSignal()
  45         self.reset = ResetSignal()
  46
  47         self.handle_trap = Signal()
  48         self.trap_handled = Signal()
  49         self.ft_action = Signal(fetch_action)
  50         self.dc_action = Signal(decode_action)
  51         self.dc_immediate = Signal(32)
  52         self.mcause = Signal(32)
  53         self.mepc = Signal()
  54         self.mpie = Signal()
  55         self.mie = Signal()
  56         self.ft_output_pc = Signal(32)
  57         self.load_store_misaligned = Signal()
  58
  59         s = [self.mpie.eq(self.mie),
  60              self.mie.eq(0),
  61              self.mepc.eq(Mux(self.ft_action == FA.noerror_trap,
  62                            self.ft_output_pc + 4,
  63                            self.ft_output_pc))]
  64
  65         # fetch action ack trap
  66         i = If(self.ft_action == FA.ack_trap,
  67                 self.mcause.eq(cause_instruction_access_fault)
  68               )
  69
  70         # ecall/ebreak
  71         i = i.Elif((self.dc_action & DA.trap_ecall_ebreak) != 0,
  72                 self.mcause.eq(Mux(self.dc_immediate[0],
  73                                 cause_machine_environment_call,
  74                                 cause_breakpoint))
  75               )
  76
  77         # load
  78         i = i.Elif((self.dc_action & DA.load) != 0,
  79                 If(self.load_store_misaligned,
  80                     self.mcause.eq(cause_load_address_misaligned)
  81                 ).Else(
  82                     self.mcause.eq(cause_load_access_fault)
  83                 )
  84               )
  85
  86         # store
  87         i = i.Elif((self.dc_action & DA.store) != 0,
  88                 If(self.load_store_misaligned,
  89                     self.mcause.eq(cause_store_amo_address_misaligned)
  90                 ).Else(
  91                     self.mcause.eq(cause_store_amo_access_fault)
  92                 )
  93               )
  94
  95         # jal/jalr -> misaligned=error, otherwise jump
  96         i = i.Elif((self.dc_action & (DA.jal | DA.jalr | DA.branch)) != 0,
  97                 self.mcause.eq(cause_instruction_address_misaligned)
  98               )
  99
 100         # defaults to illegal instruction
 101         i = i.Else(self.mcause.eq(cause_illegal_instruction))
 102
 103         s.append(i)
 104
 105         self.sync += If(self.handle_trap,
 106                         [s, self.trap_handled.eq(1)]
 107                      ).Else(
 108                         self.trap_handled.eq(0)
 109                      )
 110
 111
 112 if __name__ == "__main__":
 113     example = CPUHandleTrap()
 114     print(verilog.convert(example,
 115          {
 116             example.handle_trap,
 117             example.trap_handled,
 118             example.ft_action,
 119             example.dc_immediate,
 120             example.mcause,
 121             example.mpie,
 122             example.mie,
 123             example.ft_output_pc,
 124             example.load_store_misaligned,
 125            }))