cpu_mie.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 import string
  30 from migen import *
  31 from migen.fhdl import verilog
  32 from migen.fhdl.structure import _Operator
  33
  34 from riscvdefs import *
  35 from cpudefs import *
  36
  37 class CPUMIE(Module):
  38     def __init__(self):
  39         Module.__init__(self)
  40         self.meie = Signal(name="mie_meie", reset=0)
  41         self.mtie = Signal(name="mie_mtie", reset=0)
  42         self.msie = Signal(name="mie_msie", reset=0)
  43         self.seie = Signal(name="mie_seie")
  44         self.ueie = Signal(name="mie_ueie")
  45         self.stie = Signal(name="mie_stie")
  46         self.utie = Signal(name="mie_utie")
  47         self.ssie = Signal(name="mie_ssie")
  48         self.usie = Signal(name="mie_usie")
  49
  50         for n in dir(self):
  51             if n.startswith("_"):
  52                 continue
  53             n = getattr(self, n)
  54             if not isinstance(n, Signal):
  55                 continue
  56             self.comb += n.eq(0x0)
  57
  58         self.mie = Signal(32)
  59
  60         self.sync += self.mie.eq(self.make())
  61
  62     def make(self):
  63         return Cat( self.usie, self.ssie, 0, self.msie,
  64                     self.utie, self.stie, 0, self.mtie,
  65                     self.ueie, self.seie, 0, self.meie, )
  66
  67
  68
  69 if __name__ == "__main__":
  70     example = CPUMIE()
  71     print(verilog.convert(example,
  72          {
  73            example.meie,
  74            example.mtie,
  75            example.msie,
  76            example.mie,
  77            }))