cpu_mstatus.py

   1 """
   2 /*
   3  * Copyright 2018 Jacob Lifshay
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy
   6  * of this software and associated documentation files (the "Software"), to deal
   7  * in the Software without restriction, including without limitation the rights
   8  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   9  * copies of the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in all
  13  * copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  18  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  */
  24 `timescale 1ns / 1ps
  25 `include "riscv.vh"
  26 `include "cpu.vh"
  27 """
  28
  29 import string
  30 from migen import *
  31 from migen.fhdl import verilog
  32 from migen.fhdl.structure import _Operator
  33
  34 from riscvdefs import *
  35 from cpudefs import *
  36
  37 class MStatus:
  38     def __init__(self):
  39         self.mpie = Signal(name="mstatus_mpie", reset=0)
  40         self.mie = Signal(name="mstatus_mie", reset=0)
  41         self.mprv = Signal(name="mstatus_mprv", reset=0)
  42         self.tsr = Signal(name="mstatus_tsr", reset=0)
  43         self.tw = Signal(name="mstatus_tw", reset=0)
  44         self.tvm = Signal(name="mstatus_tvm", reset=0)
  45         self.mxr = Signal(name="mstatus_mxr", reset=0)
  46         self._sum = Signal(name="mstatus_sum", reset=0)
  47         self.xs = Signal(name="mstatus_xs", reset=0)
  48         self.fs = Signal(name="mstatus_fs", reset=0)
  49         self.mpp = Signal(2, name="mstatus_mpp", reset=0b11)
  50         self.spp = Signal(name="mstatus_spp", reset=0)
  51         self.spie = Signal(name="mstatus_spie", reset=0)
  52         self.upie = Signal(name="mstatus_upie", reset=0)
  53         self.sie = Signal(name="mstatus_sie", reset=0)
  54         self.uie = Signal(name="mstatus_uie", reset=0)
  55
  56         io = set()
  57         for n in dir(self):
  58             if n.startswith("_"):
  59                 continue
  60             n = getattr(self, n)
  61             if not isinstance(n, Signal):
  62                 continue
  63             io.add(n)
  64         self.io = io
  65
  66
  67 class CPUMStatus(Module, MStatus):
  68
  69     def __init__(self):
  70         MStatus.__init__(self)
  71         Module.__init__(self)
  72
  73         self.mstatus = Signal(32)
  74
  75         for io in self.io:
  76             if io.name_override != self.mpp.name_override:
  77                 self.comb += io.eq(0x0)
  78         self.comb += self.mpp.eq(0b11)
  79         self.comb += self.mstatus.eq(self.make())
  80
  81         self.io = set({self.mstatus, self.mpie, self.mie})
  82
  83     def make(self):
  84         return Cat(
  85                 self.uie, self.sie, Constant(0), self.mie,
  86                 self.upie, self.spie, Constant(0), self.mpie,
  87                 self.spp, Constant(0, 2), self.mpp,
  88                 self.fs, self.xs, self.mprv, self._sum,
  89                 self.mxr, self.tvm, self.tw, self.tsr,
  90                 Constant(0, 8),
  91                 (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2))
  92                 )
  93
  94 if __name__ == "__main__":
  95     example = CPUMStatus()
  96     print(verilog.convert(example, example.io))