add Makefile for verilog compilation
[rv32.git] / main_test.v
1 /*
2 * Copyright 2018 Jacob Lifshay
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in all
12 * copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 *
22 */
23 `timescale 1ns / 100ps
24
25 module main_test;
26
27 // Inputs
28 reg clk;
29 reg switch_2;
30 reg switch_3;
31
32 // Outputs
33 wire [7:0] vga_r;
34 wire [7:0] vga_g;
35 wire [7:0] vga_b;
36 wire vga_hsync;
37 wire vga_vsync;
38 wire vga_blank;
39 wire vga_pixel_clock;
40 wire led_1;
41 wire led_3;
42
43
44 // Instantiate the Unit Under Test (UUT)
45 main uut (
46 .clk(clk),
47 .vga_r(vga_r),
48 .vga_g(vga_g),
49 .vga_b(vga_b),
50 .vga_hsync(vga_hsync),
51 .vga_vsync(vga_vsync),
52 .vga_blank(vga_blank),
53 .vga_pixel_clock(vga_pixel_clock),
54 .switch_2(switch_2),
55 .switch_3(switch_3),
56 .led_1(led_1),
57 .led_3(led_3)
58 );
59
60 initial begin
61 // Initialize Inputs
62 $dumpvars;
63 clk = 0;
64 switch_2 = 0;
65 switch_3 = 0;
66
67 // Add stimulus here
68
69 forever #10 clk = ~clk;
70 end
71
72 reg [7:0] r;
73 reg [7:0] g;
74 reg [7:0] b;
75
76 always @(posedge vga_pixel_clock) begin
77 r = vga_r;
78 g = vga_g;
79 b = vga_b;
80 end
81
82 endmodule
83