main_test.v

   1 /*
   2  * Copyright 2018 Jacob Lifshay
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in all
  12  * copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  17  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  *
  22  */
  23 `timescale 1ns / 100ps
  24
  25 module main_test;
  26
  27         // Inputs
  28         reg clk;
  29
  30         // Outputs
  31         wire [7:0] vga_r;
  32         wire [7:0] vga_g;
  33         wire [7:0] vga_b;
  34         wire vga_hsync;
  35         wire vga_vsync;
  36         wire vga_blank;
  37         wire vga_pixel_clock;
  38
  39         // Instantiate the Unit Under Test (UUT)
  40         main uut (
  41                 .clk(clk),
  42                 .vga_r(vga_r),
  43                 .vga_g(vga_g),
  44                 .vga_b(vga_b),
  45                 .vga_hsync(vga_hsync),
  46                 .vga_vsync(vga_vsync),
  47                 .vga_blank(vga_blank),
  48                 .vga_pixel_clock(vga_pixel_clock)
  49         );
  50
  51         initial begin
  52                 // Initialize Inputs
  53                 clk = 0;
  54
  55                 // Add stimulus here
  56
  57         forever #10 clk = ~clk;
  58         end
  59
  60     reg [7:0] r;
  61     reg [7:0] g;
  62     reg [7:0] b;
  63
  64     always @(posedge vga_pixel_clock) begin
  65         r = vga_r;
  66         g = vga_g;
  67         b = vga_b;
  68     end
  69
  70 endmodule
  71